2V1000 Search Results

6SLX25-2

Abstract: 3s1000-5 SPARTAN-6 image processing 3S100 DSP48A DSP48E 6SLX25 "motion jpeg" dcm verilog code
Contextual Info: Baseline ISO/IEC 10918-1 JPEG Compliance Programmable Huffman Tables two DC, two AC and JPEG-D Programmable quantization tables (four) Baseline JPEG Decoder Core Up to four color components (optionally extendable to 255 components) Supports all possible scan configurations and all JPEG formats

3S1000FG456-4C

Abstract: PCI64 vhdl code for 8 bit parity generator vhdl code for parity checker 2-S200
Contextual Info: LogiCORE PCI64 Interface v3.0 DS205 April 14, 2003 Introduction LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec. Features •

fpga frame buffer vhdl examples

Abstract: 3308I pci to dual port ram interface
Contextual Info: EP430ASYN PCI Host Bridge March 14, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core Eureka Technology, Inc. 4962 El Camino Real, Suite 108 Los Altos, CA 94022 USA Phone: +1 650-960-3800 Fax: +1 650-960-3805 E-Mail: info@eurekatech.com

XC2V1000 Pin-out

Abstract: Virtex-II MAKING A10 BGA matrix m21 IEEE1532 XC2V1000 XC2V1500 XC2V250 XC2V40 XC2V500
Contextual Info: Virtex-II 1.5V Field-Programmable Gate Arrays R DS031-1 v1.7 October 2, 2001 Advance Product Specification Summary of Virtex -II Features • Industry First Platform FPGA Solution • IP-Immersion Architecture - Densities from 40K to 8M system gates

DS423

Abstract: DS211
Contextual Info: OPB Timebase WDT v1.00a DS423 December 2, 2005 Product Specification 0 0 Introduction LogiCORE Facts This document describes the specifications for a 32-bit free-running timebase and watchdog timer core for the On-Chip Peripheral Bus (OPB). The TimeBase

2S100PQ208

Abstract: 2S200EPQ208-6C 2S50PQ208-5C 2S50PQ208 PCI32 PCI64 2S100EPQ208-6C 2S50PQ208-5 2S100PQ208-5C 2s200pq208-5
Contextual Info: LogiCORE PCI32 Interface v3.0 DS 206 v1.2 July 19, 2002 Introduction Data Sheet, v3.0.100 LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized, fully PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec.

open LVDS deserialization IP

Abstract: DS243 crc verilog code 16 bit RAPIDIO
Contextual Info: RapidIO 8-bit Port Physical Layer v3.0.2 DS243 February 10, 2005 Product Specification Introduction LogiCORE Facts The LogiCORE RapidIO Physical Layer Interface, a fixed-netlist solution for the RapidIO interconnect, is a pre-implemented and fully tested module for Xilinx

Contextual Info: RapidIO 8-bit Port Physical Layer Interface June 7, 2001 Product Specification LogiCORE Facts Resources Used Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: support.xilinx.com

data encryption standard vhdl

Abstract: V400-6 XIP2031 ISE4 V400E-8
Contextual Info: Triple DES Encryption Core January 29, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core CAST, Inc. Documentation Design File Formats 11 Stonewall Court Woodcliff Lakes New Jersey 07677 USA Phone: +1-201-391-8300

3 to 8 line decoder vhdl IEEE format

Abstract: 2 to 4 line decoder vhdl IEEE format jpeg decompression algorithm XCV300 3 to 8 bit decoder vhdl IEEE format verilog code for huffman coding V300-8 image processing verilog code
Contextual Info: FASTJPEG_BW Decoder July 27, 2001 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core BARCO SILEX Rue du bosquet 7 B-1348 Louvain-la-Neuve BELGIUM Phone: +32 10 45 49 04 Fax: +32 10 45 46 36 E-mail: geert.decorte@barco.com

baud rate generator vhdl

Abstract: fifo generator xilinx spartan XILINX FIFO UART XILINX UART lite uart vhdl vhdl code for 8 bit ODD parity generator DS422 uart vhdl code fpga 2V100 UART using VHDL
Contextual Info: OPB UART Lite v1.00b DS422 December 2, 2005 Product Specification Introduction LogiCORE Facts This document describes the specifications for a UART core for the On-Chip Peripheral Bus (OPB). The UART Lite is a module that attaches to the OPB. Features

Contextual Info: Virtex-II 1.5V Field-Programmable Gate Arrays R DS031-3 v1.5 April 23, 2001 Advance Product Specification Virtex -II Electrical Characteristics Virtex-II devices are provided in -4, -5, and -6 speed grades, with -6 having the highest performance. commercial device). However, only selected speed grades

XAPP779

Abstract: UG156 SRL16 voter UG002 XQR2V6000 XQR2V1000 2V1000
Contextual Info: Application Note: Virtex-II FPGAs R XAPP779 v1.1 February 19, 2007 Summary Correcting Single-Event Upsets in Virtex-II Platform FPGA Configuration Memory Authors: Brendan Bridgford, Carl Carmichael, Chen Wei Tseng Designers of space-based application must be concerned with the effect of single-event upsets

RAM16X8

Abstract: verilog hdl code for triple modular redundancy 37101 verilog/verilog code for lvds driver xc2v3000fg sot 23-5 marking code H5 BT 342 project xc2v250cs144 XC2V3000FF1152 fpga JTAG Programmer Schematics
Contextual Info: Virtex-II Platform FPGA Handbook R R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. "Xilinx" and the Xilinx logo are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.

PCI64

Abstract: verilog hdl code for parity generator
Contextual Info: LogiCORE PCI64 Interface v3.0 DS 205 v1.2 July 19, 2002 Introduction Data Sheet, v3.0.100 LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec.

SPARTAN-3 XC3S400

Abstract: SPARTAN-3 XC3S1000 3S200 xilinx XC3S200A 2S100 XC3S50A XC3S500E Virtex-II V1000 4VLX25 SPARTAN-II xc2s200
Contextual Info: FPGA CONFIGURATORS AT18F Series FPGA Configuration Flash Memory The AT18F Series of JTAG In-System Programmable Configuration PROMs configurators provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays (FPGAs). The

transistor 6c x

Abstract: XC2V1000FG XC2VP20FF1152-6C
Contextual Info: LogiCORE PCI-X Interface v5.0 DS 208 November 11, 2004 Product Specification v5.0.87 Features LogiCORE Facts PCI-X64/66 with PCI64/33 Resource Utilization 1 • Fully PCI-X 2.0 Mode1 compliant core, 64-bit, 133/66 MHz interface with 3.3 V operation • PCI v3.0-compliant core up to 33 MHz

on digital code lock using vhdl mini pr

Abstract: XC2V3000-BG728 ternary content addressable memory VHDL XC2V6000-ff1152 TRANSISTOR 841 toshiba smd marking code transistor land pattern BGA 0,50 XC2V3000-FG676 BT 342 project smd marking code mfw
Contextual Info: Virtex-II Platform FPGA User Guide R R The Xilinx logo shown above is a registered trademark of Xilinx, Inc. ASYL, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Spartan, Timing Wizard, TRACE, Virtex, XACT, XILINX, XC2064, XC3090, XC4005, XC5210, and XC-DS501 are registered trademarks of Xilinx, Inc.

V1000FG680

Abstract: 2S200FG456-6C verilog hdl code for parity generator 2S300EFG456-6C PCI64 vhdl code for pci express V300BG432 2S100 V1000EFG680-6C vhdl code for 32bit parity generator
Contextual Info: LogiCORE PCI64 Interface v3.0 Interface Data Sheet December 14, 2001 Data Sheet, v3.0.090 LogiCORE Facts Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com

FLUKE 8840a specification

Abstract: FLUKE 8840a 700013 Y8101 capacitor IH 104j FLUKE 83RF PROBE FLUKE 79 series II multimeter diagram 40 HMR 20 EQUIVALENT 40 RB 120 8840A instruction manual U804
Contextual Info: DIGITAL MULTIMETER Instruction Manual FLUKE. 8840A DIGITAL MULTIMETER Instruction Manual PN 879304 December 1991 Rev. 2, 4/94 1994 Fluke Corporation. All rights reserved. Printed in U.S.A. All product names are trademarks of their respective companies FLUKE

RAMB16

Abstract: RAMB18X2SDP verilog for 8 point dct in xilinx what the difference between the spartan and virtex RAMB18X2 huffman decoder verilog RAMB18X2s
Contextual Info:  Conforms to the spatial LJPEG-D Lossless JPEG Decoder Core sequential lossless encoding mode (SOF3) of the ISO/IEC 10918-1 standard (CCITT T.81 recommendation).  Standalone operation. o ISO/IEC 10918-1 JPEG stream input. o Decoded pixel samples out-

vhdl code for sdram controller

Abstract: MT46V8M16 PC133 registered reference design sdram controller
Contextual Info: MC-XIL-SDRAMDDR DDR SDRAM Controller July 12, 2002 Product Specification AllianceCORE Facts Core Specifics See Table 1 Provided with Core MemecCoreTM Product Line 9980 Huennekens Street San Diego, CA 92121 Americas:+1 888-360-9044 Europe: +1 41 0 32 374 32 00

XAPP623

Contextual Info: POS-PHY Level-4 Core v5.0 DS209 August 7, 2002 Product Specification LogiCORE Facts Features • Fully compliant with OIF-SPI4-02.0 System Packet Interface Level-4 SPI-4 Phase 2 standard • Supports POS, ATM, and Ethernet 10 Gbps applications • Delivered through CORE Generator providing easy

XC4VSX25-FF668

Abstract: XC4VLX25-FF668 xc4vlx25ff668 XC2V1000-FG456 XC4VSX35-FF668-10 XC4VFX20-FF672 XC4VSX35FF668
Contextual Info: ? PCI-X Interface v5.0 DS208 August 31, 2005 Product Specification v5.0.101 Features LogiCORE Facts PCI-X64/66 with PCI64/33 Resource Utilization 1 • Fully PCI-X 2.0 Mode 1 compliant LogiCORE , 64-bit, 133/66 MHz interface with 3.3 V operation • PCI 3.0-compliant core up to 33 MHz