ROCKETIO Search Results

XAPP662

Abstract: PPC405 XAPP138 XAPP660 XAPP661 XC2VP20 FF1152 FF672 Virtex-II Platform FPGA Complete All Four Module verilog code of prbs pattern generator
Contextual Info: Application Note: Virtex-II Pro Family R XAPP662 v1.1 July 3, 2003 Summary In-Circuit Partial Reconfiguration of RocketIO Attributes Author: Vince Eck, Punit Kalra, Rick LeBlanc, and Jim McManus This application note describes in-circuit partial reconfiguration of RocketIO transceiver

Contextual Info: ` Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.4.1 March 24, 2003 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIO™ embedded

RX-2C G

Abstract: tx2c transmitter TX 2E 1240 picosecond tx-2b equivalent Gigabyte 848 TX-2B RX-2B ROSENBERGER RX_2B XENPAK70
Contextual Info: Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide UG076 v4.1 November 2, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

vhdl code scrambler

Abstract: verilog code for fibre channel decoder.vhd lanex XAPP687 vhdl code for clock and data recovery vhdl code for scrambler descrambler
Contextual Info: Application Note: Virtex-II and Virtex-II Pro Devices R 64B/66B Encoder/Decoder Author: Nick McKay and Matt DiPaolo XAPP687 v1.0 November 21, 2003 Summary This application note describes the encoding and decoding blocks of the 64B/66B encoding scheme. This application allows designs to use the RocketIO transceiver of the

verilog code for serial multiplier

Abstract: XAPP656 sequential multiplier Vhdl 8 bit sequential multiplier VERILOG RocketIO
Contextual Info: Application Note: Virtex-II Pro Family Using the Virtex-II Pro RocketIO MGT for Frequency Multiplication R XAPP656 v1.0 November 5, 2004 Summary The Virtex-II Pro RocketIO™ multi-gigabit transceiver (MGT) is extremely useful to the system designer in its usual role as a high-speed serial communications device. Many designs,

vhdl code for deserializer

Abstract: XAPP670 RocketIO ML321 RXRECCLK verilog code for fibre channel vhdl code for DCM
Contextual Info: Application Note: Virtex-II Pro Family R XAPP670 v1.0 June 10, 2003 Summary Minimizing Receiver Elastic Buffer Delay in the Virtex-II Pro RocketIO Transceiver Author: Jeremy Kowalczyk This application note describes a design that reduces latency through the receive elastic buffer

MP21608S221A

Abstract: UG198 FERRITE-220 GTX tile oversampling recovered clock ROSENBERGER verilog code for linear interpolation filter aurora GTX BLM15HB221SN1 gearbox rev maxim DVB
Contextual Info: Virtex-5 FPGA RocketIO GTX Transceiver User Guide UG198 v2.1 November 17, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

ff1136

Abstract: MGTRXP0 ROCKETIO UG196 UG351 VIRTEX-5 DS202 UG198 XC5VLX110T-FF1136 XC5VFX70TFF1136 gtx
Contextual Info: Virtex-5 FPGA RocketIO Transceiver Signal Integrity Simulation Kit User Guide for Synopsys HSPICE UG351 v2.2 May 28, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

XAPP759

Abstract: verilog code for fibre channel 1000BASE-X PPC405 Virtex-II Pro and Virtex-II Pro X Platform FPGAs Xuint32 CPCS BOARD POWER SUPPLY ML323 1000base-x xilinx DS264
Contextual Info: Application Note: Virtex-II Pro Family R Configurable Physical Coding Sublayer Author: Dai Huang, Jack Lo, and Shalin Sheth XAPP759 v1.1 March 4, 2005 Summary This application note describes a Configurable Physical Coding Sublayer (CPCS) reference design that extends the functionality of the Xilinx RocketIO multi-gigabit transceiver (MGT)

switching power supply design

Abstract: DIODE C18 ph 48v power supply XAPP946 ph c30 diode sot-223 package ph code TPS54110PWP TPS54610 TPS54610PWP TPS73625
Contextual Info: Application Note: Virtex-4 Family R XAPP946 v1.0.1 August 14, 2006 Summary Switching Power Supplies for Virtex-4 RocketIO MGTs Author: Justin Gaither This document presents design techniques and reference circuits that power Virtex -4 FX RocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.

2VP4-FG456

Abstract: Reconfiguration JTGC405TCK JTGC405TDI JTGC405TMS PPC405 XAPP660 XC2VP20 XC2VP30 XC2VP40
Contextual Info: Application Note: Virtex-II Pro Family R XAPP660 v2.2 February 4, 2004 Dynamic Reconfiguration of RocketIO MGT Attributes Author: Derek R. Curd Summary This application note describes a pre-engineered design module for Virtex-II Pro devices that enables dynamic reconfiguration of RocketIO™ Multi-Gigabit Transceiver (MGT) attributes.

free verilog code of prbs pattern generator

Abstract: verilog code 16 bit LFSR in PRBS pattern generator lfsr galois prbs using lfsr lfsr fibonacci XAPP661 verilog code for 10 gb ethernet verilog code 8 bit LFSR verilog HDL program to generate PWM
Contextual Info: Application Note: Virtex-II Pro Family R RocketIO Transceiver Bit-Error Rate Tester Author: Dai Huang and Michael Matera XAPP661 v2.0.2 May 24, 2004 Summary This application note describes the implementation of a RocketIO transceiver bit-error rate tester (BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s) between

ug196

Abstract: johnson tiles GTX tile oversampling recovered clock XC5VLX30T-FF323 aurora GTX ROSENBERGER XC5VSX50TFF665 2F-15 UCF virtex-4 BLM15HB221SN1
Contextual Info: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.0 June 10, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

HP-461A

Abstract: HP461A RocketIO LTM4604 LTM4616 LTM8023
Contextual Info: News Release ⎜ www.linear.com DC/DC uModule Regulator Family Verified by Xilinx for High Speed RocketIO SERDES MILPITAS, CA – March 23, 2009 – Linear Technology Corporation announces that four of its low noise DC/DC uModule regulators have been verified by Xilinx to power multigigabit

Contextual Info: Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.3 November 20, 2002 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIO™ embedded

J132 regulator

Abstract: ML525 VIRTEX-5 DDR2 pcb design J135 ff1136 ML523 am2 SOCKET PIN LAYOUT diode ak38 e48 connector ESD Pushbutton data sheet
Contextual Info: ML52x User Guide Virtex-5 FPGA RocketIO Characterization Platform UG225 v2.0 April 17, 2008 R 0402527-03 R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

vhdl code for uart communication

Abstract: XC2VP50
Contextual Info: ` Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.4.1 March 24, 2003 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIO™ embedded

vhdl code for uart communication

Abstract: XC2VP50 XC2VP70 FF1704 pinout
Contextual Info: ` Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.4.1 March 24, 2003 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIO™ embedded

infiniband Physical Medium Attachment

Abstract: CX27201 TLK3101 VSC7123 VSC7216-01 XC2VP20 XC2VP30 XC2VP40 XC2VP70 SIGNAL PATH DESIGNER
Contextual Info: White Paper: Virtex-II Pro Family R WP160 v1.1 October 22, 2002 Emulating External SERDES Devices with Embedded RocketIO Transceivers By: Matt DiPaolo The Virtex-II Pro Platform FPGA provides an attractive single-chip solution to serial transceiver design problems that previously required multiple

vhdl code for demultiplexer

Abstract: RRUS 01 BBU RRU free source code for cdma transceiver using vhdl obsai vhdl code for demultiplexer 8 to 1 using 4 to 1 vhdl code for demultiplexer for 1 to 8 using 1 to 4 vhdl code lte remote rf RRUS
Contextual Info: OBSAI v1.1 DS612 August 8, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE OBSAI core implements an OBSAI RP3 interface supporting RP3-01 at 768 MB, 1.5 Gbps, and 3 Gbps per second using RocketIO™ GTP Transceivers available for Virtex™-5 FPGAs. The OBSAI core

UG196

Abstract: MP21608S221A xc5vlx30t-ff323 XC5VLX155T-FF1738 XC5VSX50TFF665 direct sequence spread spectrum virtex-5 FERRITE-220 FF1136 XC5VLX30T-FF665 XC5VLX110T-FF1738
Contextual Info: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.1 December 3, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

UG198

Abstract: DS601 ROCKETIO vhdl code for pci express OC48 UG204 XILINX PCIE aurora GTX Virtex - II Family FPGA virtex ucf file 6
Contextual Info: Virtex-5 FPGA RocketIO GTX Transceiver Wizard v1.4 DS601 June 27, 2008 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP RocketIO™ GTX Transceiver Wizard automates the task of creating HDL wrappers 1 to configure the high-speed serial GTX

cmos 556 timer

Abstract: powerpc 405 system ace compactflash solution for virtex 4 verilog code for 10 gb ethernet Virtex-II Pro XC2VP40 XC2VP100 digital clock vhdl code FF672 multi channel UART controller using VHDL 16 bit Array multiplier code in VERILOG
Contextual Info: ` 8 Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v3.1.1 March 9, 2004 Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty RocketIO™ embedded multi-gigabit

ML421

Abstract: 2310 fx ML320 ML423 ML325 sp002 DS083 DS112 ML321 ML323
Contextual Info: Aurora v3.0 DS128 September 19, 2008 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP Aurora core implements the Aurora protocol on Virtex -II Pro and Virtex-4 FX FPGAs. The core can use up to 20 Virtex-II Pro or 24 Virtex-4 FPGA RocketIO™ multi-gigabit transceivers