RECONFIGURATION Search Results

intel embedded microcontroller handbook

Abstract: RG-11/U COM20020 COM20020D CQM20020 RG62 COM20020B
Contextual Info: COM20020D PRELIMINARY STANDARD MICROSYSTEMS CORPORATION COM20020 ULANC Revision D Universal Local Area Network Controller with 2K X 8 On-Board RAM FEATURES • • • • • • • • • • • New Features for Rev. D • Data Rates up to 5 Mbps Programmable Reconfiguration Times

75176B

Abstract: COM20019I COM20019I-HD COM20019ILJP COM20020
Contextual Info: COM20019I Low Cost ARCNET ANSI 878.1 Controller with 2K x 8 On-Board RAM Datasheet Product Features Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory New Features: − Data Rates up to 312.5 Kbps − Programmable Reconfiguration Times

Contextual Info: Dynamic Reconfiguration in Stratix V Devices 6 2013.05.06 SV52008 Subscribe Feedback The transceiver reconfiguration controller offers several different dynamic reconfiguration modes. You can choose the appropriate reconfiguration mode that best suits your application needs. All the dynamic

Contextual Info: Reconfiguration Timings for AnadigmApex VDD RESETb ERRb goes low if missing or corrupt inverse sync byte detected ERRb Open Drain Continuous clock max freq = 40MHz ACLK Reconfiguration start Reconfiguration end Reconfiguration becomes active if in automatic

USB2524

Abstract: 56-PIN QFN-56 USB2524-ABZJ 4 port usb2.0 hub
Contextual Info: USB2524 USB MultiSwitchTM Hub PRODUCT FEATURES „ Datasheet USB2.0 Compatible 4-Port Hub with two upstream host port connections „ — Provides electronic reconfiguration and re-assignment of any of its 4 downstream ports to either of two upstream host ports “on-the-fly” .

COM20019I

Abstract: COM20019I-DZD COM20019I-HD COM20019I-HT COM20019ILJP
Contextual Info: COM20019I Low Cost ARCNET ANSI 878.1 Controller with 2K x 8 On-Board RAM Datasheet Product Features ƒ New Features: ƒ − Data Rates up to 312.5 Kbps − Programmable Reconfiguration Times Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory

XAPP879

Abstract: UG382 Spartan-6 FPGA DCM_CLKGEN
Contextual Info: Application Note: Spartan-6 Family PLL Dynamic Reconfiguration Author: Karl Kurbjun and Carl Ribbing XAPP879 v1.0 May 13, 2010 Summary This application note provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the Spartan -6 FPGA Phase Locked Loop (PLL) through its

SPARTAN XC2S50

Abstract: 18V02 xilinx 8 pin dip Xilinx XC2V500 XILINX SPARTAN XC2S50 18V512 18V00 SPARTAN 6 Configuration FPGA Virtex 6 pin configuration 17S00A
Contextual Info: Xilinx Configuration PROMs XC18V00, XC17V00, XC17S00 FPGA Configuration PROMs 180V00 PROM Family Based on the Xilinx state-of-the-art ISP PROM architecture and manu- • PROM-triggered FPGA reconfiguration via JTAG factured on an advanced 0.35m • Up to 264 MHz configuration speed

Contextual Info: Ordering number : ENA2341 LV25810PEB Bi-CMOS LSI http://onsemi.com Car DSP Tuner Overview LV25810PEB is a DSP tuner LSI which adopts Low-IF. This IC has realized not only the significant reduction of external parts compare to the existing model by integration, but also the reconfiguration of specification according to

HYC9088

Abstract: COM20020I COM20020I3V-HD COM20020ILJP3V COM20020IP3V RG62 NDS322
Contextual Info: COM20020I 3.3V COM20020I 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM FEATURES New Features Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory - Data Rates up to 5 Mbps - Programmable Reconfiguration Times

xc4000 pin

Abstract: XAPP093 XC3000 XC3020A XC4000 XC4025E XC4085XL XC5200
Contextual Info: APPLICATION NOTE R XAPP093 November 10, 1997 Version 1.1 Dynamic Reconfiguration 14* Application Note by Peter Alfke Introduction Important Considerations All Xilinx SRAM-based FPGAs can be in-system configured and re-configured an unlimited number of times.

COM20019

Abstract: COM20019I COM20019I-HD COM20019ILJP COM20019IP COM20020 RG62* belden
Contextual Info: COM20019I Low Cost ARCNET ANSI 878.1 Controller with 2K x 8 On-Board RAM FEATURES • • • • • • • • • • • New Features Data Rates up to 312.5 Kbps Programmable Reconfiguration Times 24 Pin DIP, 28 Pin PLCC, 48 Pin TQFP Packages Ideal for Industrial/Factory/Building

HYC9088

Abstract: COM20020 COM20020D RG62
Contextual Info: COM20020D COM20020 ULANC Revision D Universal Local Area Network Controller with 2K x 8 On-Board RAM FEATURES • • • • • • • • • • • New Features for Rev. D Data Rates up to 5 Mbps Programmable Reconfiguration Times 24 Pin DIP, 28 Pin PLCC Package

XC6200

Abstract: XC3000 XC3020A XC4000 XC4025E XC4085XL XC5200 xc1700family
Contextual Info: APPLICATION NOTE APPLICATION NOTE  XAPP 093 November 10, 1997 Version 1.1 Dynamic Reconfiguration 13* Application Note by Peter Alfke Introduction Important Considerations All Xilinx SRAM-based FPGAs can be in-system configured and re-configured an unlimited number of times. The

XC17000

Abstract: XC3000 XC4000 XC2000 XC3000A XC3100 XC3100A XC4000A XC4000D XC4000H
Contextual Info: Configuration Control Pin Connections in T 36 he following recommendations guarantee a well-defined beginning for any FPGA configuration or reconfiguration process — after the initialization and clearing of the configuration memory in all FPGAs has been completed, and the

Contextual Info: Ordering number : EN*A2315 LV25810UEB Advance Information http://onsemi.com Bi-CMOS LSI Car DSP Tuner Overview LV25810UEB is a DSP tuner LSI which adopts Low-IF. This IC has realized not only the significant reduction of external parts compare to the existing model by integration, but also the reconfiguration of specification according to

XAPP151

Abstract: virtex user guide 1999 XCV100 XCV1000 XCV150 XCV200 XCV300 XCV400 XCV50 XCV600
Contextual Info: Virtex Configuration Architecture Advanced Users’ Guide R XAPP151 September 30,1999 Version 1.2 Application Note by Steve Kelem Summary The Virtex architecture supports powerful new configuration modes, including partial reconfiguration. These mechanisms are designed to give

flash memory vhdl code

Abstract: ORCA fpga vhdl code for multiplexer 32 to 1 16bit microprocessor using vhdl vhdl code up down counter vhdl code for n bit generic counter vhdl code for multiplexer 8 to 1 using 2 to 1 vhdl code for memory controller vhdl code for multiplexer 16 to 1 using 4 to 1 in 4 bit microprocessor using vhdl software
Contextual Info: Using a Lattice CPLD and Flash Memory to Configure an SRAM-Based FPGA October 2003 Reference Design RD1017 Introduction SRAM-based FPGA devices are volatile and require reconfiguration on power-up cycles. FPGA external configuration data must be held on a non-volatile device. For systems incorporating a microprocessor or host computer system, configuration data may be stored on a system’s local hard drive with a host-run application used to configure

Contextual Info: RapidIO Dynamic Data Rate Reconfiguration Reference Design for Stratix IV GX Devices AN-617-1.0 Application Note The RapidIO dynamic data rate reconfiguration reference design demonstrates how to use the ALTGX_RECONFIG megafunction to reconfigure the RapidIO MegaCore®

chang capacitor

Abstract: Xilinx XC3090 XC3090 XC4005
Contextual Info: Metalithic Systems Exploits Real-Time T he Xilinx Reconfigurable Computing Developer’s Program is promoting the commercial use of FPGAs in Rapid Reconfiguration RR, also known as reconfigurable computing applications. These systems add significant value by

chang capacitor

Abstract: XC3090 XC4005
Contextual Info: Metalithic Systems Exploits Real-Time T he Xilinx Reconfigurable Computing Developer’s Program is promoting the commercial use of FPGAs in Rapid Reconfiguration RR, also known as reconfigurable computing applications. These systems add significant value by

Contextual Info: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions AN-661-3.0 Application Note This application note describes the flow for implementing fractional phase-locked loop PLL reconfiguration and dynamic phase shifting for fractional PLLs in 28-nm

8051 interface with rs485

Abstract: 2kx8 rom 75176b
Contextual Info: COM20020I Rev D Universal Local Area Network Controller with 2K x 8 On-Board RAM Datasheet Product Features ƒ New Features for Rev. D ƒ − Data Rates up to 5 Mbps − Programmable Reconfiguration Times Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory

Contextual Info: COM20020 3.3V COM20020 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM FEATURES !" New Features !" Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory - Data Rates up to 5 Mbps - Programmable Reconfiguration Times