SPARTAN XC2S50
Abstract: 18V02 xilinx 8 pin dip Xilinx XC2V500 XILINX SPARTAN XC2S50 18V512 18V00 SPARTAN 6 Configuration FPGA Virtex 6 pin configuration 17S00A
Contextual Info: Xilinx Configuration PROMs XC18V00, XC17V00, XC17S00 FPGA Configuration PROMs 180V00 PROM Family Based on the Xilinx state-of-the-art ISP PROM architecture and manu- • PROM-triggered FPGA reconfiguration via JTAG factured on an advanced 0.35m • Up to 264 MHz configuration speed
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xc18v00xc17v00xc17s00180v00+1318v00256kb44-pin20-pinspartan xc2s5018v02xilinx 8 pin dipxilinx xc2v500xilinx spartan xc2s5018v512spartan 6 configurationfpga virtex 6 pin configuration17s00a
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