TP24 Search Results

TP2435

Contextual Info: TP2435 Die Specification Pad Layout 1 0,0 2 Backside: Drain Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 55 55 11 ± 1.5 Au 1 (mils) TP2435 1 (mils) Back Side Bonding Pad Material Bond Wire Bond Wire Size Drain Al/Cu/Si

Contextual Info: TP2435 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

Contextual Info: TP2424 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

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Contextual Info: TP2424 TP2424 Low Threshold Pre-Release Information P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package BVDSS / RDS ON VGS(th) ID(ON) BVDGS (max) (max) (min) TO-243AA* -240V 8.0Ω -2.4V -800mA TP2424N8 * Same as SOT-89.

Contextual Info: TP2435 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling

DATE CODE FOR SUPERTEX

Abstract: TP2424 TP2424N8 TP2424ND
Contextual Info: TP2424 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package BVDSS / RDS ON VGS(th) BVDGS (max) (max) (min) TO-243AA* Die -240V 8.0Ω -2.4V -800mA TP2424N8 TP2424ND * Same as SOT-89. ID(ON) Product supplied on 2000 piece carrier tape reels.

TP242

Abstract: TP236 TP238 TP239 TP240 TP243
Contextual Info: Steel Switch Boxes 31/2" DEEP SWITCH BOXES – GANGABLE – 18.0 CUBIC INCH CAPACITY 2" WIDE x 3" LONG FOR NONMETALLIC CABLE – CLAMPS IN EACH END Steel Boxes TP236 TP238 TP239 TP242 TP243 Cat. # Bracket Ground Pigtail Ears TP236 TP238 TP239 TP240 TP242

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Abstract: ISL6401 C551 ISL5587 caller id single chip Refac SLIC DIAGRAM
Contextual Info: ISL5587 Dual Ringing SLIC May 2002 PR O DU CT O VE RV IEW FN6027 /Title Description HC55 The ISL5587 Dual Ringing SLIC is a High Voltage Line Interface Device for providing POTS over Broadband 80, applications. Two ISL5587 Dual Ringing SLICs are used C551 together with the TP2450 Quad Programmable Codec from

TP2424

Contextual Info: TP2424 Die Specification Pad Layout 1 0,0 2 Backside: Drain Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 55 55 11 ± 1.5 Au 1 (mils) TP2424 1 (mils) Back Side Bonding Pad Material Bond Wire Bond Wire Size Drain Al/Cu/Si

Contextual Info: Supertex inc. TP2424 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description ►► Low threshold ►► High input impedance ►► Low input capacitance ►► Fast switching speeds ►► Free from secondary breakdown ►► Low input and output leakage

TP2424

Contextual Info: Supertex inc. TP2424 Die Specification Pad Layout 1 0,0 2 Backside: Drain Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 55 55 11 ± 1.5 Au 1 (mils) TP2424 1 (mils) Back Side Bonding Pad Material Drain Al/Cu/Si Bonding Pad Description

A254735

Abstract: TP2010L TP201 TP241 TP2410L
Contextual Info: SILICONIX INC SûE t • 0254735 0Q1727Û TP2010L, TP2410L P-Channel Enhancement-Mode MOS Transistors 7tlb ■ SIX fTSEconix in c o r p o r a te d 'T* vi-zs PRODUCT SUMMARY TO-92 TO-226AA V (BR)DSS PART NUMBER BOTTOM VIEW ■d (A) '" s r TP2010L -200 10

Contextual Info: TP2424 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

texas instruments circuit diagram

Abstract: Ring Tone Generator TP2450
Contextual Info: TP2450 QUAD PROGRAMMABLE COMBO Rev 1.0E 11/27/01 • Single chip codec and filter to handle four CO or PABX channels • Seamless Interface to McBSP of C54x or C6x DSP • Meets the relevant CCITT/ITU, EIA and LSSGR recommendations • Interface to Intersil Harris ISL5587 dual

TP249

Abstract: TP244 TP252 TP246 TP248 TP250 TP254
Contextual Info: Steel Switch Boxes 31/2" DEEP SWITCH BOXES – GANGABLE – 18.0 CUBIC INCH CAPACITY Steel Boxes 2" WIDE x 3" LONG FOR ARMORED & METAL CLAD MCI CABLE – CLAMPS IN EACH END TP244 TP249 TP246 KNOCKOUTS Each Side Cat. # Bracket Ground Pigtail Ears Each End

TP2435

Contextual Info: TP2435 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TP2424

Abstract: TP2424N8
Contextual Info: TP2424 TP2424 Low Threshold Pre-Release Information P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Order Number / Package BVDSS / RDS ON VGS(th) ID(ON) BVDGS (max) (max) (min) TO-243AA* -240V 8.0Ω -2.4V -800mA TP2424N8 * Same as SOT-89.

TP2435

Abstract: TP2435N8 TP2435NW
Contextual Info: TP2435 TP2435 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information * Order Number / Package BVDSS / RDS ON VGS(th) ID(ON) BVDGS (max) (max) (min) TO-243AA* Die* -350V 15Ω -2.4V -800mA TP2435N8 TP2435NW Same as SOT-89. Product supplied on 2000 piece carrier tape reels.

VP2410

Contextual Info: VPDV24 P-Channel Enhancement-Mode MOSFETs TYPE PACKAGE Single TO-92 TO-226AA • BS208 TP2410L, TP2010L VP2410L Single Chip • Available as VPDV2CHP SÖ.xd DEVICE TYPICAL CHARACTERISTICS O u tp u t C h a ra cte ristics fo r Low G a te Drive (m A) -2 -3

Contextual Info: TP241 Linear ICs dc-to-dc/Charge Pump Voltage Converter status Military/High-RelN Output Voltage Nominal V 5.0 Load Current Max. (A)300m Drop-Out Volt Max. P(D) Max. (W) Nom. Supp (V)48 Minimum Operating Temp (øC)-25 Maximum Operating Temp (øC)71 Package StyleModule

TP2435

Contextual Info: Supertex inc. TP2435 Die Specification Pad Layout 1 0,0 2 Backside: Drain Die Specifications Die Dimensions Device Length Width Thickness mils Back Side Metal 55 55 11 ± 1.5 Au 1 (mils) TP2435 1 (mils) Back Side Bonding Pad Material Drain Al/Cu/Si Bonding Pad Description

TP2424

Contextual Info: TP2424 P-Channel Enhancement Mode Vertical DMOS FETs Features General Description ► ► ► ► ► ► This low threshold enhancement-mode normally-off transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This

TP2435

Abstract: TP2435N8 TP2435NW
Contextual Info: TP2435 Low Threshold P-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information * Order Number / Package BVDSS / RDS ON VGS(th) ID(ON) BVDGS (max) (max) (min) TO-243AA* Die* -350V 15Ω -2.4V -800mA TP2435N8 TP2435NW Same as SOT-89. Product supplied on 2000 piece carrier tape reels.

Contextual Info: TP2483 Transistors Si NPN Lo-Pwr BJT Military/High-RelN V BR CEO (V)60 V(BR)CBO (V)60 I(C) Max. (A)500m Absolute Max. Power Diss. (W)400m Maximum Operating Temp (øC) I(CBO) Max. (A)10n @V(CBO) (V) (Test Condition) V(CE)sat Max. (V) @I(C) (A) (Test Condition)