TOV12 Search Results

80960CA

Abstract: Non-Pipelined Single-Cycle processor 80960CA-16 80960CA-25 270710
Contextual Info: SPECIAL ENVIRONMENT 80960CA-25 -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR  Two Instructions Clock Sustained Execution  Four 59 Mbytes s DMA Channels with Data Chaining  Demultiplexed 32-bit Burst Bus with Pipelining Y 32-bit Parallel Architecture Two Instructions clock Execution

Contextual Info: 80960RP 1.0 1.2 ABOUT THIS DOCUMENT Terminology In this document, the following terms are used: This data sheet contains ADVANCE INFORMATION about Intel’s i960 RP processor, including a func­ tional overview, mechanical data package signal locations and simulated thermal characteristics ,

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: in te i 0 M F [ i3 [m Y 0 N 80960CF-33, -25,-16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • S o c k e t and O b jec t C o d e C o m p atib le w ith 8 0 96 0C A • T w o In s tru c tio n s /C lo c k S u stain ed E xecu tion • F ou r 59 M b y te s /s D M A C h an n els w ith D ata Chaining

Non-Pipelined processor

Abstract: 80960CF 80960CA intel packaging handbook 240800 80960CF-33 80960CF-40 Non-Pipelined Single-Cycle processor 270710
Contextual Info: A PRELIMINARY 80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR • ■ ■ ■ ■ ■ • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining

CCL-HL832HS

Abstract: intel strataflash j3 PXA263 278639 EME-G770 HL832HS PXA250 and PXA210 manual PXA262 PXA26x PXA210
Contextual Info: Intel PXA26x Processor Family Electrical, Mechanical, and Thermal Specification Data Sheet Product Features • ■ ■ ■ ■ ■ ■ ■ High-Performance Processor — Intel® XScale Microarchitecture — 7 stage pipeline — 32 KB instruction cache

socket am3 pinout

Abstract: socket AM2 pinout AM3 Processor Functional INTEL 80960 pipeline architecture 80960RM
Contextual Info: Intel 80960RM I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.2 Universal 5 V and 3.3 V PCI Signalling Environment (C-stepping only) Data Sheet Product Features ■ ■ ■ ■ High Performance Intel® 80960JT Core ■ —Sustained One Instruction/Clock Execution

540L

Contextual Info: 80960RM I/O Processor • Complies with PCI Local Bus Specification, Revision 2.1 ■ 5 K PCI Signalling Environment Data Sheet Advance Information Product Features ■ High Performance 80960JT Core ■ — Sustained One Instruction/Clock Execution — 16 Kbyte, Two-Way Set-Associative

PPC401GF-MA50C2

Abstract: PowerPC 401
Contextual Info: PowerPC 401GF 32-Bit RISC Embedded Controller Features • PowerPC R ISC CPU core and instruction set architecture • Pipelined CPU core runs at up to 4X the external bus clock rate • Separate instruction cache and write-back/ write-through data cache, both two-way setassociative

270710

Abstract: CX041A
Contextual Info: ^ 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR * Two Instructions/Clock Sustained Execution * Four 59 Mbytes/s DMA Channels with Data Chaining * Dem ultiplexed 32-bit Burst Bus with Pipelining • 32-bit Parallel Architecture — Two Instructions/clock Execution

chromerics

Abstract: OV26 80960JF 80960RP AD10 AD11 MA11 272736 27248 i960RP
Contextual Info: ADVANCE INFORMATION i960 RP I/O PROCESSOR • 33 MHz, 5.0 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification Revision 2.1 • High Performance 80960JF Core ■ ■ ■ ■ ■ DMA Controller — Sustained One Instruction/Clock Execution

intel G31 circuit diagram

Abstract: intel 845 circuit diagram all chip socket AM2 pinout P5 microarchitecture socket am3 pinout Thermocouple K bead type am3 socket pin diagram am3 socket pinout intel 845 SERVICE MANUAL intel p30
Contextual Info: Intel 80312 I/O Companion Chip Datasheet Product Features • ■ ■ ■ Core Interface Unit —100 MHz Request Bus —Data Bus shared with Intel® 80200 processor and SDRAM —4-Entry Request Buffer PCI-to-PCI Bridge Unit —Primary and Secondary 66 MHz/64-bit

PXA255

Abstract: PXA255 jtag flash programming JTAG PXA255 flash programming PXA255 flash programming 17x17mm 278693 lcd N7 PXA255 ic diagram PXA250 intel PXA255
Contextual Info: Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification Data Sheet Product Features • ■ ■ ■ High Performance Processor — Intel® XScale Microarchitecture — 32 KB Instruction Cache — 32 KB Data Cache — 2 KB “mini” Data Cache

powerpc 403gcx

Abstract: 403GCX PPC403GCX tis14
Contextual Info: PowerPC 403GCX 32-Bit RISC Data Sheet Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • 16KB instruction cache and 8KB writeback data cache, two-way set-associative

273414

Contextual Info: Intel 80200 Processor based on Intel® XScale Microarchitecture Datasheet Advance Information Product Features • ■ ■ ■ High Performance Processor based on Intel® XScale™ Microarchitecture — 7-8 stage Intel® Superpipelined Technology — 32-Entry Instruction Memory

NHPXA270C5

Abstract: LUPXA255A0C400 LUPXA255A0E400 LUPXA255A0 nhPXA270C5C520 LUPXA255 LUPXA255A GDPXA255A0E200 LUPXA255A0C200 FWPXA270C5E416
Contextual Info: Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification Data Sheet Product Features • ■ ■ ■ High Performance Processor — Intel® XScale Microarchitecture — 32 KB Instruction Cache — 32 KB Data Cache — 2 KB “mini” Data Cache

540-lead

Abstract: 273328
Contextual Info: Intel 80960RS I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.2 Universal 5 V and 3.3 V PCI Signalling Environment (C-stepping only) Data Sheet Advance Information Product Features ■ ■ ■ ■ High Performance Intel® 80960JT Core

Contextual Info: ADVANCE INFORMATION i960 RP I/O PROCESSOR • 33 MHz, 5.0 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification Revision 2.1 High Performance 80960JF Core — Sustained One Instruction/Clock Execution — 4 Kbyte Two-Way Set-Associative

B1859

Abstract: PPC401 PPC401GF-MC50C2 PPC401GF PPC401GFMA50C2 TIS11 401GF MA-506 B1166 ibm powerpc 401gf
Contextual Info: PowerPC 401GF 32-Bit RISC Embedded Controller Data Sheet Features • PowerPC RISC CPU core and instruction set architecture • Pipelined CPU core runs at up to 4X the external bus clock rate • Separate instruction cache and write-back/ write-through data cache, both two-way setassociative

272737

Abstract: 80960JF 80960RD 80960RP AD10 AD11 MA11 27248
Contextual Info: ADVANCE INFORMATION i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS • • • • 33 MHz, 3.3 Volt Version 80960RP 33/3.3 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core Complies with PCI Local Bus Specification Revision 2.1 5 Volt PCI Signalling Environment

80960JT

Abstract: 80960VH AD10 MA11 273179
Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

i486 sx

Abstract: 80960CX 80960JF 80960RD 80960RP 272736 272918 INTEL386 pipeline architecture
Contextual Info: Intel i960® RX I/O Processor at 3.3 Volts Datasheet • 33 MHz, 3.3 Volt Version 80960RP 33/3.3 • 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core • Complies with PCI Local Bus Specification, Revision 2.1 • 5 Volt PCI Signalling Environment

socket am3 pinout

Abstract: 80960RN am3 socket pin diagram socket AM2 pinout 80960JT PAR64 REQ64 GC80960RN100
Contextual Info: Intel 80960RN I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.2 Universal 5 V and 3.3 V PCI Signalling Environment (C-stepping only) Data Sheet Advance Information Product Features ■ ■ ■ ■ High Performance Intel® 80960JT Core

socket am3 pinout

Abstract: socket AM3 pinout diagram 80960RN socket AM2 pinout am3 socket pin diagram am3 socket pinout GC80960RN100
Contextual Info: Intel 80960RN I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.2 Universal 5 V and 3.3 V PCI Signalling Environment (C-stepping only) Data Sheet Product Features ■ ■ ■ ■ High Performance Intel® 80960JT Core ■ —Sustained One Instruction/Clock Execution