TGD13 Search Results

mr 4020

Abstract: H606 SY100H606 SY10H606 SY10H606JC VCCE13
Contextual Info: REGISTERED HEX * p r e l im in a r y T T L -T O -P E C L TRANSLATO R 1 S Y N c rfU Y SEMICONDUCTOR SY10H606 SY100H606 DESCRIPTION FEATURES • Differential 50 £2 ECL outputs ■ Choice between differential PECL or TTL clock input ■ Single +5V power supply

Contextual Info: * 8-BIT SYNCHRONOUS BINARY UP COUNTER SYNERGY SY10E016 SY100E016 SEMICONDUCTOR FEATURES DESCRIPTION The SY10E016 and SY100E016 are high-speed synchronous, presettable and cascadable 8-bit binary counters designed for use in new, high-performance ECL systems. Architecture and operation are the same as the

Contextual Info: A SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE e V W C D / 'V sE ^ ooXd u c to r C lo c k w o rk s SY10H842 SY100H842 DESCRIPTION FEATURES • Translates positive ECL to TTL PECL-to-TTL ■ 300ps pin-to-pin skew ■ 500ps part-to-part skew

Contextual Info: V SYNERGY ClockWorks PRELIMINARY in fo r m a tio n SY89421L HIGH PERFORMANCE PHASE LOCKED LOOP SEMICONDUCTOR FEATURES DESCRIPTION • 1.12GHz maximum VCO frequency ■ 30 to 560MHz reference input operating frequency ■ External 2.5GHz VCO capability ■ Low jitter differential design

Contextual Info: * L O W V O LTA G E 1:9 D IF F E R E N T IA L E C L /P E C L C L O C K D R IV E R C V A in r V S W IC W D u n -O R FEATURES DESCRIPTION 200ps part-to-part skew 50ps output-to-output skew Differential design Vbb output Voltage and temperature compensated outputs

Contextual Info: SYNERGY PRELIMINARY SY10EL16 SY100EL16 d i f f e r e n t i a l r e c e iv e r SEMICONDUCTOR DESCRIPTION FEATURES • 250ps propagation delay The SY10EL/100EL16 are differential receivers. The devices are functionally equivalent to the E116 devices, with higher performance capabilities. With output transition

100HF646

Abstract: ATT10 H600 H646 0D023
Contextual Info: SING LE SUPPLY OCTAL SYNERGY Clockworks P EC L/TTL-to-TTL S E M IC O N D U C T O R FEA TU R E S S Y 100 H 646 5 Y1 ° ° H 6 4 6 D ES C R IPTIO N I PECL/TTL-to-TTL version of popular ECLinPS El 11 I Meets specifications required to drive high­ performance x86 processors

Contextual Info: « SYNERGY C lockw orks PRELIMINARY FREQUENCY SYNTHESIZER SY89429 SEMICONDUCTOR DESCRIPTION FEATU R ES The SY89429 is a general purpose, synthesized clock source targeting applications that require both serial and parallel interfaces. Its Internal V co will operate over a range

Contextual Info: S IN G L E S U P P L Y P E C L ' T T L s U s a w & & Y 1 : 4 c l o c k FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ d r i v e CIO CSkvToHk8S4 2 r s y i ° o h 8 4 2 DESCRIPTION Translates positive ECL to TTL PECL-TTL 300ps pin-to-pin skew Guaranteed skew spec

Contextual Info: * QUINT DIFFERENTIAL LINE RECEIVER SYNERGY SEMICONDUCTOR FEATURES • ■ Max. propagation delay of 900ps ■ Differential outputs ■ I ee min. of -6 0 m A ■ ESD protection of 2000V ■ Extended supply voltage option: V ee = -4 .2 V to -5 .5 V ■ Voltage and tem perature com pensation for

E336

Abstract: SY100E337 SY10E337
Contextual Info: A 3-BIT SCANNABLE SYNERGY t r a n s c b v e r BUS S E M IC O N D U C T O R 1 DESCRIPTION FEATURES 1500ps max. clock to bus data transmit 10OOps max. clock to Q (data receive) Extended 100E V ee range of -4.2V to -5.5V 25Q cutoff bus outputs 50£2 receiver outputs

SY10ELT22L

Abstract: SY100ELT22L SY10ELT22LZC
Contextual Info: V PRELIMINARY SY10ELT22L SY100ELT22L d u a l t t l -t o - d if f e r e n t ia l SYNERG Y PECL TRANSLATOR SEMICONDUCTOR DESCRIPTION FEATURES The SY10ELT/100ELT22L are dual TTL-to-differential PECL translators. Because PECL Positive ECL levels are used, only +3.3V and ground are required. The small

e104

Abstract: SY100E104 SY10E104 SY10E104JC
Contextual Info: • QUINT 2-INPUT AND/NAND GATE SYNERGY SY10E104 SY100E104 SEMICONDUCTOR FEA TU RES D E S C R IP T IO N 600ps max. propagation delay True and complementary outputs OR/NOR function outputs ESD protection of 2000V Fully compatible with Industry standard 10KH,

Contextual Info: * 9-BIT LATCH ECL-TTL TRANSLATOR SYNERGY SEMICONDUCTOR FEATURES SY10H603 SY100H603 DESCRIPTION • 9-bit ideal for byte-parity applications ■ 3-state TTL outputs ■ ESD protection of 2000V ■ Flow-through configuration ■ Extra TTL and ECL power/ground pins to minimize

Contextual Info: – T H E C H A L L E N G E R I N B U I L D I N G A U T O M A T I O N R E G I N – T H E C H A L L E N G E R I N B U I L D I N G A U T O M A T I O N Box 116, S-428 22 Kållered, Phone: +46 31 720 02 00 info@regin.se Sweden Fax: +46 31 720 02 50 www.regin.se

F100K

Abstract: SY100S341
Contextual Info: * 8-BIT SHIFT REGISTER SYNERGY SY100S341 SEMICONDUCTOR FEATURES • ■ ■ ■ D E S C R IP T IO N Max. shift frequency of 600MHz Max. Clock to Q delay of 1200ps lEEmln. of-150m A ESD protection of 2000V The SY100S341 offer eight D-type, edge-triggered flip­

SY100H601

Abstract: SY10H601 SY10H601JC
Contextual Info: « c y A /C D /^ v 9 -B IT E C L -T O -T T L s E lc O N M C T C M SY10H601 W IT H 3 ' S T A T E E N A B L E FEATURES SY100H601 DESCRIPTION I 9-bit ideal for byte-parity applications 3-state TTL outputs T he SY10/100H601 are 9-bit, dual supply ECL-to-TTL translators. Devices in the S ynergy 9-bit tran sla to r series