TABLE20 Search Results

TRANSISTOR mcr 100-8

Contextual Info: MOTOROLA MC33389 SEMICONDUCTOR TECHNICAL DATA SBC System basis chip Advance Information Automotive System Basis Chip The MC33389 is a monolithic integrated circuit combining many functions frequently used by automotive ECUs. It incorporates a low speed fault

Contextual Info: iPEM 2.4 Gb SDRAM-DDR2 AS4DDR232M72PBG 32Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES BENEFITS DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • 255 Plastic Ball Grid Array PBGA , 25 x 32mm

laptop motherboard chip level crb

Abstract: CL-GD5320 LAPTOP Motherboard CHIP LEVEL book GD610 CL-GD610 gd5320 GD6340 gd510 CL-GD6410 cirrus logic gd610
Contextual Info: CL-GD6420 Data Book FEATURES • Single-chip VGA controller ■ Pin-compatible with the CL-GD6410 in 2-DRAM applications High-Resolution LCD VGA Controller for Notebook Computers ■ Up to 1 Mbyte 2, 4, or 8 256K x 4 DRAM Video Memory ■ Extended resolution up to 1024 x 768 with 256 colors on

Contextual Info: Lattica ispLSI and pLSI 1032 ;Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers

Contextual Info: Lattice ispLSr 1032 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs

Contextual Info: W3H32M72E-XSB2X W3H32M72E-XSB2XF 256MB – 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES BENEFITS  Data rate = 667, 533, 400  69% space savings vs. FPBGA  Package:  Reduced part count • 208 Plastic Ball Grid Array PBGA , 16 x 20mm

Contextual Info: W3H264M16E-XBX ADVANCED* 256MB – 2 x 64M x 16 DDR2 SDRAM 79 PBGA FEATURES BENEFITS  Data rate = 400 Mb/s, 533 Mb/s, 667 Mb/s*  Larger ball pitch for higher reliability  Package:  Footprint compatible with W3H64M16E • 79 Plastic Ball Grid Array PBGA , 11 x 14mm

DNU-A13

Contextual Info: W3H64M16E-XBX 128MB – 64M x 16 DDR2 SDRAM 79 PBGA FEATURES BENEFITS  Data rate = 400 Mb/s, 533 Mb/s  Larger ball pitch for higher reliability  Package:  Pinout compatible with 2-Rank Version • 79 Plastic Ball Grid Array PBGA , 11 x 14mm

Contextual Info: DUAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT IDT82V2082 FEATURES: • • • • • • • - Dual channel T1/E1/J1 long haul/short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays

Contextual Info: i PEM 2.1 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR232M64PBG 32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit BENEFITS FEATURES „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp

CHN 703

Abstract: CHN G4 112
Contextual Info: IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT FEATURES ♦ ♦ ♦ ♦ ♦ ♦ ♦ Fully integrated octal T1/E1 short haul line interface which supports 100Ω T1 twisted pair, 120Ω E1 twisted pair and 75Ω E1 coaxial applications Selectable single rail or dual rail mode and AMI or HDB3/B8ZS

spdif jack 6 pin

Abstract: VRM Section of laptop Motherboard INTEL 845 MOTHERBOARD CIRCUIT diagram STAC9700 STAC9721 STAC9750 STAC9752 STAC9753 STAC9756 STAC9766
Contextual Info: DATASHEET TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING Description IDT's STAC9752/9753 are general purpose 20-bit, full duplex, audio CODECs conforming to the analog component specification of AC'97 Audio CODEC 97

W3H32M72E-XSBX

Abstract: calibration definition
Contextual Info: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Programmable CAS latency: 3, 4, 5, or 6 Package: Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

S3F828BX

Abstract: S3F8285X S3F8289X
Contextual Info: S3C828BX/F828BX /C8289X/F8289X /C8285X/F8285X 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.5 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no

446H

Abstract: 451H RDN11 GR-253-CORE GR-499-CORE IDT82P2821 640-Pin
Contextual Info: 21 +1 Channel High-Density T1/E1/J1 Line Interface Unit IDT82P2821 Version 3 February 6, 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775 Printed in U.S.A.

package detail of IDT82V2081

Abstract: IDT82V2081 TQFP44 TQFP44 package
Contextual Info: SINGLE CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT IDT82V2081 FEATURES: • • • • • • • Single channel T1/E1/J1 long haul/short haul line interfaces Supports HPS Hitless Protection Switching for 1+1 protection without external relays

Contextual Info: White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Programmable CAS latency: 3, 4, 5, or 6 „ Package: „ Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

Contextual Info: Lattice ispLSr and pLSI 1032 I Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers

Contextual Info: INVERSE MULTIPLEXING FOR ATM IDT82V2608 Version - 2 December 8, 2003 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • • FAX: (408) 492-8674 Printed in U.S.A. 2003 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

ether H5

Abstract: futaba vfd 9 GP1219A01A Futaba VFD display futaba vfd circuit diagram 256X64 Futaba VFD futaba 4 digit Futaba protocol futaba display 126
Contextual Info: TENTATIVE VACUUM FLUORESCENT DISPLAY MODULE ENGINEERING PROPOSAL GP1219A01A EVALUATION □ ACCEPTED WITHOUT ANY CHANGE □ THE FOLLOWING CHANGE IS REQUIRED April 1 , 2008 Engineering Group Electronic Components Division ISSUED Yasuo Ohno BY CHECKED BY CHECKED

Contextual Info: White Electronic Designs W3H32M64E-XSBX 32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES „ Data rate = 667, 533, 400 „ Write latency = Read latency - 1* tCK „ Package: „ Commercial, Industrial and Military Temperature Ranges „ Organized as 32M x 64, user configurable as 2 x

W3H32M72E

Abstract: BA0BA12
Contextual Info: White Electronic Designs W3H32M72E-XSBX 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES  Data rate = 667, 533, 400  Programmable CAS latency: 3, 4, 5, or 6  Package:  Posted CAS additive latency: 0, 1, 2, 3 or 4 • 208 Plastic Ball Grid Array PBGA , 18 x 20mm

1032-60LJ

Abstract: 1032-60LJI 1032-60LTI 1032-90LJ 1032-90LT smd JSs 13 smd JSs 24
Contextual Info: Lattice ispLSI 1032 I Semiconductor I Corporation In-System Programmable High Density PLD Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers

hy5rs123235b

Abstract: HY5RS123235BFP HY5RS123235
Contextual Info: HY5RS123235BFP 512Mbit 16Mx32 GDDR3 SDRAM HY5RS123235BFP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.