SELF REFRESH TEMPERATURE Search Results

Contextual Info: $67&589.49 3 89#589.ð49#&026#'5$0#+IDVW#SDJH#PRGH, )HDWXUHV • Refresh • Organization: 262,144 words by 16 bits • High speed - 512 refresh cycles, 8 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - Self-refresh option is available for new generation device

VG264265

Abstract: VG264260B
Contextual Info: VG264260BJ 262,144x16-Bit CMOS Dynamic RAM VIS TRUTH TABLE 2-CKE Notes: 1-4 CKEn-1 CKE n CURRENT STATE COMANDn ACTIONn L L Power-Down X Maintain Power-Down Self Refresh X Maintain Self Refresh Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5 Self Refresh

Contextual Info: ADVANCE MT4 L C2M8A1/2 S 2 MEG x 8 DRAM I^IICRON 2 MEG x 8 DRAM 5.0V, SELF REFRESH (MT4C2M8A1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8A1/2 S) FEATURES PIN ASSIGNMENT (Top View) • SELF REFRESH, i.e. "Sleep Mode" • Industry standard x8 pinouts, timing, functions and

Contextual Info: AS4C256K16E0 5V 256Kx 16 CMOS DRAM EDO Features • Refresh - 5 1 2 refresh cycles, 8 m s refresh interval - RAS-only o r CAS-before-RAS refresh o r self-refresh - Self-refresh o p tio n is available for n e w g en eratio n device • O rganization: 2 6 2 ,1 4 4 w o rd s x 16 bits

AS4LC4M4E1-60JC

Abstract: AS4LC4M4E0-50JC AS4LC4M4E0-50JI AS4LC4M4E0-50TC AS4LC4M4E0-50TI AS4LC4M4E0-60JC AS4LC4M4E0-60JI
Contextual Info: March 2001 AS4LC4M4E0 AS4LC4M4E1 4Mx4 CMOS DRAM EDO Family Features • Refresh - 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0 - 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1 - RAS-only or CAS-before-RAS refresh or self-refresh

Contextual Info: ADVANCE MT4 L C1M16CX S 1 MEG X 16 DRAM IURN blllSHT I3004b21 4HT p ilC R O N MICRON TECHNOLOGY INC SSE » DRAM X 1 6 D R A M m 1 M E G 5.0V SELF REFRESH (MT4C1M16CX S) 3.0/3.3V, SELF REFRESH (MT4LC1M16CX S) FEATURES PIN ASSIGNMENT (Top View) • Self Refresh, ie "Sleep Mode"

Contextual Info: MICRON SEMICONDUCTOR INC b3E D • blllSH^ □□□77A3 B4T « M R N ADVANCE MT4 L C2M8B1/2 S 2 MEG X 8 WIDE DRAM MICRON I SEMICONDUCTOR. INC WIDE DRAM 2 MEG X 8 DRAM 5.0V SELF REFRESH (MT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES • SELF REFRESH, or "Sleep Mode"

Contextual Info: ADVANCE MT4 L C2M8B1/2 S 2 MEG x 8 DRAM I^ IC Z R O N 2 MEG x 8 DRAM 5.0V SELF REFRESH (MT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES PIN ASSIGNMENT (Top View) • SELF REFRESH, i.e. "Sleep M ode" • Industry standard x8 pinouts, tim ing, functions and

Contextual Info: February 2001 Advance Information AS4LC4M4E0 AS4LC4M4E1 4Mx4 CMOS DRAM EDO Family Features • Refresh - 4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0 - 2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1 - RAS-only or CAS-before-RAS refresh or self-refresh

96-ball FBGA

Contextual Info: 2Gb: x8, x16 DDR3Lm SDRAM Description 1.35V DDR3Lm SDRAM MT41K256M8 – 32 Meg x 8 x 8 banks MT41K128M16 – 16 Meg x 16 x 8 banks Description Features • • • • • • Self refresh temperature SRT Automatic self refresh (ASR) Write leveling Multipurpose register

AS4LC4M4E1-60JC

Abstract: AS4LC4M4E1-50JC AS4LC4M4E1-50JI AS4LC4M4E1-50TC AS4LC4M4E1-50TI AS4LC4M4E1-60JI AS4LC4M4E1-60TC AS4LC4M4E1-60TI
Contextual Info: April 2001 AS4LC4M4E1 4Mx4 CMOS DRAM EDO 3.3V Family Features • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ

Contextual Info: May 2001 AS4LC4M4E1 4Mx4 CMOS DRAM EDO 3.3V Family Features • Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh • TTL-compatible, three-state I/O • JEDEC standard package - 300 mil, 24/26-pin SOJ

A43L3616V-6

Abstract: A43L3616
Contextual Info: A43L3616 2M X 16 Bit X 4 Banks Synchronous DRAM Features n n n n n Clock Frequency: 166MHz @ CL=3 143MHz @ CL=3 n Burst Read Single-bit Write operation n DQM for masking n Auto & self refresh n 64ms refresh period 4K cycle n 54 Pin TSOP (II) n Low Self Refresh Current version for –V grade

AS4LC4M4F1-50JC

Abstract: AS4LC4M4F1-50JI AS4LC4M4F1-50TC AS4LC4M4F1-50TI AS4LC4M4F1-60JC AS4LC4M4F1-60JI AS4LC4M4F1-60TC
Contextual Info: May 2001 AS4LC4M4F1 4Mx4 CMOS DRAM Fast Page 3.3V Family Features • Refresh • Organization: 4,194,304 words × 4 bits • High speed - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh - 50/60 ns RAS access time

s1866

Contextual Info: 4Gb: x4, x8, x16 DDR3L-RS SDRAM Description 1.35V DDR3L-RS SDRAM MT41K1G4 - 128 Meg x 4 x 8 banks MT41K512M8 – 64 Meg x 8 x 8 banks MT41K256M16 – 32 Meg x 16 x 8 banks Description Features • Self refresh temperature SRT • Automatic self refresh (ASR)

Refresh

Contextual Info: TECHNICAL NOTE Low Power Function of Mobile RAM Auto Temperature Compensated Self Refresh ATCSR CAUTION This document describes Auto Temperature Compensated Self Refresh (ATCSR), one of low power functions that have been adapted to Mobile RAM. All related operations and numerical values in this technical note are examples for reference only.

Contextual Info: IBM11S1325L 1M x 32 SODIMM Module Features cations. Low active current consumption All inputs & outputs are LVTTL 3.3V or TTL(5V) compatible Extended Data Out (EDO) access cycle Refresh Modes: RAS-Only, CBR, Hidden Refresh and Self Refresh 1024 refresh cycles distributed across 128ms

RR 113001

Abstract: 1M16E5
Contextual Info: Advance information •■ AS4VC1M16E5 A 2.5V lM x 16 CMOS lntelliwatt,v DRAM EDO Features 1 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh 1Read-modify-write

Contextual Info: January 2001 Advance Information AS4VC256K16EO 2.5V 256K X 16 CMOS DRAM EDO Features • EDO page mode • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh

400J

Contextual Info: SIEMENS 16M X 4-Bit Dynamic RAM 4k & 8k Refresh hYB 3164400J/T -50/-60 HYB 3165400J/T -50/-60 Prelim inary Inform ation 7.2 mW standby (TTL) 720 nW standby (MOS) _ Read, write, read-modify-write, CAS-beforeRAS refresh (CBR), RAS-only refresh, hidden refresh and self

AS4LC256K16EO

Contextual Info: AS4LC256K16EO 3.3V 256K X 16 CMOS DRAM EDO Features • 5V I/O tolerant • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 words x 16 bits • High speed - RAS-only or CAS-before-RAS refresh or self refresh - 45/50/60 ns RAS access time

Contextual Info: Advance information •■ AS4SC1M 16E5 A 1,8V 1M x 16 C M O S Intelliwatt1'' DRAM EDO Features • Organization: 1,048,576 words x 16 bits • High speed • 1 0 2 4 refresh cycles, 16 m s refresh interval - RAS-only or CAS-before-RAS refresh or self refresh

Contextual Info: Advance information •■ AS4VC256K16E0 A 2.5V 256KX 16 CMOS DRAM EDO Features • 512 refresh cycles, 8 ms refresh interval • Organization: 262,144 w ords x 16 bits - RAS-only or CAS-before-RAS refresh or self refresh • H ig h speed - 45/60 ns KAS access tim e

DRAM 4464

Abstract: MX-1610 4464 memory 4464 dram
Contextual Info: IBM11S1320LN IBM11S1320LL 1 M x 3 2 S O D IM M M odule Features • All inputs & outputs are TTL 5V or LVTTL(3.3V) compatible • Fast Page Mode access cycle • Refresh Modes: RAS-Only, CBR, Hidden Refresh and Self Refresh • 1024 refresh cycles distributed across 128ms