RRIDE Search Results

RK90E

Abstract: overcurrent relay inverse normal curves RRIDE RRIDE41 overcurrent relay inverse RRTIE BS142 RK 92-1 E RK475 asea relay
Contextual Info: Catalogue RK 47-3 E EA Edition 1 January 1972 File R, P a rt2 Time-lag over-current relay type RRIDE 4 • Single-phase or three-phase design, 50— 60 Hz • Inverse o r independent tim e-lag char­ acteristic • A djustable instantaneous operation fo r high ove r-currents

74LS73

Abstract: pin diagram of 7473 74LS73 dual JK 74H73 7473 JK flip flop 7473 pin diagram 7473 Flip-Flop 7473 N7473F N7473N
Contextual Info: 54/7473 54H/74H73 54LS/74LS73 LOGIC SYMBOL 14 — DESCRIPTION 12 1 -0 > C P J O 13 10 - IO — ¥ IO 3 — Q The Reset R d is an a syn ch ro n o u s active LO W input. W hen LOW, it ove rrides the C lock and data inpu ts fo rc in g the Q o u tp u t LO W and the Q o u tp u t HIGH.

74H101

Abstract: N74H101F N74H101N S54H101F S54H101W
Contextual Info: 54H/74H101 LOGIC SYMBOL A 5 DESCRIPTION The “ 101” is a JK N egative E dge -T rig gere d F lip-F lo p fe a tu rin g A N D -O R gated_JK in­ puts and a d ire c t Set inpu t. Th e Set S d is an a s y n c h ro n o u s active LOW input. W hen LOW, the So ove rrides th e c lo c k and data

H102

Abstract: H102 D 1 N74H102F N74H102N S54H102F S54H102W 74H102
Contextual Info: D E S C R IP T IO N T he “ 102” is a JK N egative E dge -T rig gered F lip -F lo p w ith gated JK in p u ts and d ire c t S et and Reset inputs. Th e Set S d >and Reset (R d > are a syn ch ro n o u s active LOW inputs. W hen LOW, th e y ove rride th e c lo c k and

H103

Abstract: S54H103F cock N74H103F N74H103N S54H103W
Contextual Info: 54H/74H103 LOGIC SYMBOL DESCRIPTION The ‘'103" is a D ual JK N egative EdgeT rig gered F lip-F lo p w ith separate^ C lock and d ire c t Reset inputs. T h e R eset R d is an a syn ch ro n o u s a ctive LO W inpu t. W hen LOW, the R d ove rrides the C lock and data

dy 255

Abstract: 74s405 H R C M F 2J 225 Fairchild 9960 nixie driver 9614 line driver ci 8602 gn block diagram FJH211 Fairchild msi cul9960 variable frequency circuit diagram using IC 555
Contextual Info: IN THE, BOSTON - 6 17- 4 4 * A SUBSIDiA) ./ OF DUCOMMUN INCORPOfiATED S, MASS vw . JU N E 1 97 S Fairchild Semiconductor TTL Data Book Contents And Section Selector If you know the correct 5400, 7400, 9300 or 9600 device type number, find the correct page in the

IC LA 4127

Abstract: la 4127 P3212 8212D
Contextual Info: Am3212 *Am8212 Eight-Bit Input/Output Port Distinctive Characteristics • F u lly parallel, 8 -b it data register and b u ffe r replacing latches, m ultiplexers and buffers needed in m icro­ processor systems. • Available fo r operation over both com m ercial and

CY7C1347

Abstract: CY7C1347-166AC
Contextual Info: CY7C1347 V CYPRESS 128K X 36 Synchronous-Pipelined Cache RAM T he CY7C1347 I/O pins can operate at eith e r the 2.5V or the 3.3V level, the I/O pins are 3.3V to le ra n t w h en V ddq =2.5V. Features • S u p p o rts 1 0 0-M H z bus fo r Pentium o p e ratio n s w ith zero w ait sta tes

Contextual Info: fax id: 1080 CYPRESS 64K x 32 Synchronous-Pipelined Cache RAM PRELIMINARY sf Features Functional Description • Low 1.65 m W s ta n d b y p o w er (f=0, L ve rs io n ) • S u p p o rts 1 0 0 -M H z bus fo r P en tium and P ow erP C ™ o p e ratio n s w ith zero w a it states

lambda alpha

Abstract: alpha 250S power supply alpha 600 AW82S0S alpha400 alpha400 circuit alpha power supply alpha 600 ALPHA600 alpha 600 manual instruction Alpha 250s circuit
Contextual Info: 216 UMIBDAA M O D U LAR WA T T B O X * Muta Family M o d u la r W a tt B ox Available as multiple outputs power supply by modular configuration Model max outputs max output wattage am a250S W ham 6ch 7ch 250W 400W 600W 8Q0W mam 14ch JUpha800 DENSEI-LAMBDA

L133A

Contextual Info: CY7C1346 64K X 36 Synchronous-Pipelined Cache RAM Features The C Y 7 C 1 346 I/O pins can op era te at eith er the 2.5V o r the 3.3V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • Supports 10O-MHz bus for Pentium and PowerPC operations with zero wait states

Contextual Info: HC5517 HARRIS S E M I C O N D U C T O R Ringing SLIC Subscriber Line Interface Circuit J a n u a ry 1997 Features Description • Thru-SLIC Open Circuit Ringing Voltage up to 77VPEAK/54VRMS> 3 REN Capability at 44V rms The HC 5517 is a ringing SLIC designed to accom m odate a

Displa

Abstract: 7segm
Contextual Info: 5 4/744 8 LOGIC SYMBOL DESCRIPTION FEATURES The “ 4 8 ” is a BCD to 7-Segm ent D ecoder. It a c c e p ts 4-bit BCD da ta and provides seven a ctive HIGH d e coded outputs to drive 7-seg­ ment displa ys of various type s. It is used prim arily w ith high current or high voltage

1117 L

Abstract: DO-210 fairchild 10262 ol18 Fairchild MOS 38 1117 fairchild
Contextual Info: 3816 PROGRAMMABLE DIVIDER 3 through 262,145 G E N E R A L D E S C R IP T IO N - The 3 8 1 6 is a p ro g .a m m a b ii* c o u n te . c jp a b le o f c i i t f i n t j b y j n Y m o d u li fr o m th re e 10 2 6 2 . 14 5 (2 1 8 + i } T h e 3 8 1 6 uses o n ly n.ne leads to pro g ra m 18 bu s by «jpplym q one ol

7476 truth table

Abstract: 74ls76 jk flip-flop logic symbol and truth table jk flip flop 7476 7476 PIN DIAGRAM 7476 PIN DIAGRAM input and output pin diagram of 7476 S5476F PIN CONFIGURATION 7476 7476 7476 pin configuration
Contextual Info: 54/7476 54H/74H76 54LS/74LS76 DESCRIPTION The "76” is a D ual J K F lip -F lo p w ith in d iv id ­ ual J, K, C lock, S et and Reset inpu ts. Th e 7476 and 74H76 are p o sitive pulse trig g e re d flip -flo p s . JK in fo rm a tio n is loaded in to the m aster w h ile the C lock is H IG H and tra n s ­

C4328

Abstract: MC4341 C4339
Contextual Info: MTTL Complex Functions MOTOROLA E M O , COMPLEX FUNCTIONS M C 4 3 0 0 /M C 4 0 0 0 Series T h e M T T L c o m p le x fu n c tio n s are designed fo r d ig ita l app lication s in th e m e d iu m to high-speed range. These M T T L devices p ro vid e s ign ificant re d u c tio n in package co u n t

Contextual Info: Order this document by MC33470/D M M O TO R O LA M C 33470 Synchronous R ectification DC/DC Converter Program m able Integrated Controller T he M C 3 34 70 is a d ig ita lly p ro gra m m a ble sw itch ing vo lta g e regulator, sp e cifica lly d e sign ed fo r M icro proce ssor supply, V oltage R e gu lator M odule

PLD12

Abstract: 74LS429 N74LS429N PLD11 1N814 "FRC"
Contextual Info: 74LS429 FIFO RAM Controller FRC Preliminary Specification Logic Products FEATURES • Direct addressing up to 64K • Cascadable for addressing beyond 64K • Asynchronous Read/Write operation • 3-State address outputs • Selectable FIFO length in multiples of 2

Contextual Info: C M T T L MC5400F/7400F series DUAL J-K FLIP-FLOP MC5473F* MC7473F* J 14— C LO C K 1 -< This negative-edge-clocked dual J-K flip-flop operates on the masterslave principle. The device is quite useful for simple registers and count­ ers where multiple J and K inputs are not required.

MP8792

Contextual Info: M P8792 CMOS 12-Bit High Speed Analog-to-Digital Converter with Serial Logic Interface Port M Micro Power Systems FEATURES APPLICATIONS 12-Bit ADC With DNL = ±1 LSB, INL = ±2 LSB SNR > 60 dB Sampling Frequency < 2 MHz Internal Track and Hold: Input -3 dB Frequency = 10 MHz

7548FP

Abstract: PM7548 PM7548GP of IC OP-07 7548
Contextual Info: ÍPMI PM-7548 CMOS 8-BIT /xP COMPATIBLE 12-BIT D /A CONVERTER P r e c i s i o n M o n o l i t h i c s Inc. FEATURES • • • • • • • • • CROSS REFERENCE 8-B it Bus Com patible 12-Bit DAC Versatile M icroprocessor Interface with Selectable Data

CHN 804

Contextual Info: WTELEDYNE COMPONENTS TC804 12-BIT xP-COMPATIBLE MULTIPLEXED A/D CONVERTER FEATURES GENERAL DESCRIPTION • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ T h e T C 8 04 is a 12-bit (p lu s sign and o ver-range analog to digital con verte r. It is e q uivalen t to th e p o pular T C 7109A

ACA101

Abstract: CY7C1326 R311Q
Contextual Info: fax id: 1106 CYPRESS CY7C1326 P R E L IM IN A R Y 128K X 18 Synchronous-Pipelined Cache RAM Features Functional Description Low 1.65 m W s ta n d b y p o w er (f= 0, L ve rs io n ) S u p p o rts 10 0-M H z bus fo r P en tiu m and Pow erPC o p e ratio n s w ith zero w ait sta tes

80486 microprocessor block diagram and pin diagram

Abstract: CY7C1325 intel 80.82
Contextual Info: fax id: 1091 ADVANCED INFORMATION CY7C1325 256K x 18 Synchronous 3.3V Cache RAM Functional Description Features • S u p p o rts 117-M H z m icro p ro c ess o r c a ch e s y ste m s w ith zero w ait states T he C Y 7 C 1325 is a 3 .3 V 25 6 K by 18 synch ron ous cache RAM