CY7C1347 Search Results

CY7C1347

Abstract: CY7C1347-166AC
Contextual Info: CY7C1347 V CYPRESS 128K X 36 Synchronous-Pipelined Cache RAM T he CY7C1347 I/O pins can operate at eith e r the 2.5V or the 3.3V level, the I/O pins are 3.3V to le ra n t w h en V ddq =2.5V. Features • S u p p o rts 1 0 0-M H z bus fo r Pentium o p e ratio n s w ith zero w ait sta tes

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

CY7C1347B

Abstract: memory depth expansion
Contextual Info: CY7C1347 CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium  and PowerPC operations with zero wait states

CY7C1347D

Abstract: CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC
Contextual Info: 327 CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz 1.5 ns set-up time and 0.5 ns hold time

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

CY7C1347G-133AXI

Abstract: CY7C1347G-166BGC CY7C1347G CY7C1347G-200AXC CY7C1347G-200BGC CY7C1347G-225AXC CY7C1347G-250AXC CY7C1347G-250BGC
Contextual Info: PRELIMINARY CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

CY7C1347F

Abstract: CY7C1347F-200AC CY7C1347F-225AC CY7C1347F-225BGC CY7C1347F-250AC CY7C1347F-250BGC
Contextual Info: CY7C1347F 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache

CY7C1347

Contextual Info: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

CY7C1347D-250BGC

Abstract: CY7C1347D CY7C1347D-225BGC CY7C1347D-250AC
Contextual Info: 327 CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz 1.5 ns set-up time and 0.5 ns hold time

CY7C1347B

Contextual Info: CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

Contextual Info: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states

CY7C1347

Contextual Info: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

Contextual Info: CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features Functional Description • Fast access times: 2.5 and 3.5 ns This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell

165 ball

Abstract: CY7C1347G-133AXI AN1064 CY7C1347G
Contextual Info: CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • • • • • The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G IO pins can operate at

CY7C1347F

Contextual Info: 347F PRELIMINARY CY7C1347F 128K x 36 Pipelined Sync SRAM Features CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture

CY7C1347F

Abstract: CY7C1347F-166BGI
Contextual Info: CY7C1347F 128K x 36 Pipelined Sync SRAM Features CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Functional Description Features • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

CY7C1347

Abstract: CY7C1347-133AC
Contextual Info: fax id: 1113 PRELIMINARY CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1347 is a 3.3V 128K by 36 synchronous-pipelined cache SRAM designed to support zero wait state secondary

Contextual Info: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)

CY7C1347F

Contextual Info: 347F PRELIMINARY CY7C1347F 128K x 36 Pipelined Sync SRAM Features CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture

Contextual Info: CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Functional Description[1] Features • Fully registered inputs and outputs for pipelined operation • 128K x 36 common I/O architecture • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ)

Contextual Info: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

AN1064

Abstract: CY7C1347G
Contextual Info: CY7C1347G 4 Mbit 128K x 36 Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for Pipelined Operation ■ 128K x 36 common I/O architecture ■ 3.3V core Power Supply (VDD) ■ 2.5V/3.3V I/O Power Supply (VDDQ) ■