CY7C1346 Search Results

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

L133A

Contextual Info: CY7C1346 64K X 36 Synchronous-Pipelined Cache RAM Features The C Y 7 C 1 346 I/O pins can op era te at eith er the 2.5V o r the 3.3V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • Supports 10O-MHz bus for Pentium and PowerPC operations with zero wait states

Contextual Info: 346A PRELIMINARY CY7C1346A/GVT7164D36 64K x 36 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • The CY7C1346A/GVT7164D36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry

CY7C1346H

Abstract: CY7C1346H-166AXC
Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V/2.5V I/O operation • Fast clock-to-output times

CY7C1346

Contextual Info: fax id: 1112 PRELIMINARY CY7C1346 64K x 36 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1346 is a 3.3V 64K by 36 synchronous-pipelined cache SRAM designed to support zero wait state secondary

Contextual Info: fax id: 1112 CY7C1346 : / C Y P R E S S 64K X 36 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 m W s ta n d b y p o w er (f=0, L versio n ) • S u p p o rts 10 0 -M H z bus fo r P en tiu m and Pow erPC o p e ratio n s w ith zero w a it sta tes

Contextual Info: CY7C1346 PRELIMINARY 64K x 36 Synchronous-Pipelined Cache RAM Features T he C Y 7 C 1 346 I/O pins can o p era te at eith e r the 2.5 V o r the 3 .3 V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • S u p p o rts 1 0 0-M H z bus fo r P en tiu m and Pow erPC

Contextual Info: CY7C1346F 2-Mb 64K x 36 Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times counter for internal burst operation. All synchronous inputs are

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 38-05672 Spec Title: CY7C1346H 2-MBIT 64K X 36 PIPELINED SYNC SRAM Sunset Owner: Jayasree Nayar (NJY) Replaced by: None CY7C1346H 2-Mbit (64K x 36) Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation

A101

Abstract: CY7C1346F CY7C1346F-100AC CY7C1346F-133AC CY7C1346F-166AC
Contextual Info: CY7C1346F 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times

CY7C1346

Contextual Info: CY7C1346 PRELIMINARY nnnnnnnn,n Íi^ ^ ^ ^ ^ ~."T? 64K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1346 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC

A101

Abstract: CY7C1346F CY7C1346F-100AC CY7C1346F-133AC CY7C1346F-166AC
Contextual Info: CY7C1346F 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1346H 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1346H PRELIMINARY 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times

A101

Abstract: CY7C1346F CY7C1346F-100AC CY7C1346F-133AC CY7C1346F-166AC
Contextual Info: CY7C1346F 2-Mbit 64K x 36 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 36 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times

CY7C1346

Abstract: 7C1346L-100
Contextual Info: 1346 CY7C1346 PRELIMINARY 64K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1346 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

CY7C1346

Contextual Info: fax id: 1 1 1 2 CYPRESS PRELIMINARY CY7C1346 64K X 36 Synchronous-Pipelined Cache RAM Features Functional Description Low 1.65 m W s ta n d b y p o w er (f= 0, L ve rs io n ) S u p p o rts 10 0-M H z bus fo r P en tiu m and Pow erPC o p e ratio n s w ith zero w ait sta tes

Contextual Info: PRELIMINARY CY7C1346A/GVT7164D36 64K x 36 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • The CY7C1346A/GVT7164D36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry

ATPA

Abstract: 7130SA100P 24l01 7C263/4-35C 7164S15Y cy9122-25 7133SA35J 7142sa55 7130sa55p cy2149-45c
Contextual Info: Product Line Cross Reference CYPRESS CYPRESS CYPRESS CYPRESS CYPRESS CY2147-35C CY7C147-35C CY7C147-45C CY7C147-35C CY91L22-35C CY7C122-35C CY2147-45C CY2147-35C CY7C148-35C CY7C148-25C+ CY91L22-45C CY93L422AC CY2147-45C CY7C147-45C CY7C148-45C CY7C148-35C

1H08S

Abstract: PI6C2405A-1HW ASM706CUA SOIC-6 microchip ADM809RAR ADM705AN MAX809SEUR T ASM5P2309-1H-16-S K7N163601B MAX810JEUR
Contextual Info: Supervisors Cross Reference Guide Alliance Maxim/Dallas IMP ASM1232LP DS1232LPS-2 IMP1232LP ASM1232LPCMA DS1232LP IMP1232LPCMA ASM1232LPEMA DS1232LP IMP1232LPEMA ASM1232LPN DS1232LP IMP1232LPN Analog Devices Micrel Microchip MIC1232N TC1232CPA - - - - - -

ADM809RAR

Abstract: AS7C256A hsbga 416 lcd cross reference IDT CYPRESS CROSS REFERENCE clocks DS1232* watch dog timer Product Selector Guide mbg* sot143 FS781 IDT74SSTV16857
Contextual Info: DISCLAIMER Alliance Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Alliance Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied

Contextual Info: fax id: 1112 ^ T C Y P P g g «f 64K X PREUM,NARY C Y7C 1346 36 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states

verilog for SRAM 512k word 16bit

Abstract: CY62512V CYM74P436 192-Macrocell 62128 sram 7C1350 Triton P54C palce16v8 programming guide 7C168A intel 16k 8bit RAM chip
Contextual Info: Product Selector Guide Static RAMs Organization/Density Density X1 X4 4K X8 X9 X16 X18 X32 X36 7C148 7C149 7C150 16K 7C167A 7C168A 7C128A 6116 64K to 72K 7C187 7C164 7C166 7C185 6264 7C182 256K to 288K 7C197 7C194 7C195 7C199 7C1399/V 62256/V 62256V25 62256V18