CY7C1329 Search Results

64KX32

Abstract: 7C13 CY7C1329
Contextual Info: fax id: 1080 1CY 7C13 29 CY7C1329 PRELIMINARY 64K x 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 mW standby power (f=0, L version) The CY7C1329 is 3.3V 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary

A101

Abstract: CY7C1329G CY7C1329G-133AC CY7C1329G-166AC
Contextual Info: CY7C1329G 2-Mb 64K x 32 Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times counter for internal burst operation. All synchronous inputs are

CY7C1329

Contextual Info: CY7C1329 V CYPRESS 64K X 32 Synchronous-Pipelined Cache RAM Features • S u p p o rts 1 3 3-M H z bus fo r P en tiu m and Pow erPC o p e ratio n s w ith zero w ait sta tes • F ully reg istered inp u ts and o u tp u ts fo r pip elined operatio n • 64K x 32 co m m o n I/O arch ite ctu re

CEL9200

Abstract: 8361H A100R CY7C1329 JESD22
Contextual Info: Cypress Semiconductor Technology Qualification Report QTP# 99311 VERSION 2.0 December, 2000 R52D-3Technology, Fab 4 Qualification CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Ed Russell Reliability Director

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

Contextual Info: CY7C1329H PRELIMINARY 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times

Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times

I1415

Abstract: 64KX32 CY7C1329
Contextual Info: fax id: 1080 S b M IM Ì r i s a l i i J F PRELIMINARY F T V fS T“ ¡T* &*• ÆÊ ; U I F lm ß CY7C1329 b ö 64K X 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 m W s ta n d b y p o w er (f=0, L ve rs io n ) • S u p p o rts 1 0 0 -M H z bus fo r Pen tium and Pow erPC ™

CY7C1329

Contextual Info: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns 133-MHz

CY7C1329

Contextual Info: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Features output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns 133-MHz device . • Supports 133-MHz bus for Pentium and PowerPC operations with zero wait states

CY7C1329H

Abstract: CY7C1329H-166AXC
Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

CY7C1329

Abstract: GW 94 H
Contextual Info: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns 133-MHz

CY7C1329H

Abstract: CY7C1329H-133AXC
Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

64KX32

Abstract: CY7C1329
Contextual Info: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Features All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns 133-MHz

64KX32

Abstract: CY7C1329
Contextual Info: fax id: 1080 S b M IM Ì r i s a l i i J F PRELIMINARY F T V fS T“ ¡T* &*• ÆÊ ; U I F lm ß CY7C1329 b ö 64K X 32 Synchronous-Pipelined Cache RAM Features Functional Description • Low 1.65 m W s ta n d b y p o w er (f=0, L ve rs io n ) • S u p p o rts 1 0 0 -M H z bus fo r Pen tium and Pow erPC ™

Contextual Info: fax id: 1080 CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Featu res Funct ional Description T h e C Y 7 C 1 329 is 3.3 V 64 K by 32 synch ron ous-p ip eline d cache SR AM designed to su p p o rt zero w a it state seco nd ary cache with m inim al glue logic.

CY7C1329H

Abstract: CY7C1329H-166AXC
Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

A101

Abstract: CY7C1329G CY7C1329G-133AC
Contextual Info: CY7C1329G 2-Mb 64K x 32 Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times counter for internal burst operation. All synchronous inputs are

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description • Registered inputs and outputs for pipelined operation The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter

A101

Abstract: CY7C1329G CY7C1329G-133AC CY7C1329G-166AC
Contextual Info: CY7C1329G 2-Mb 64K x 32 Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V I/O operation • Fast clock-to-output times counter for internal burst operation. All synchronous inputs are

Contextual Info: CY7C1329H 2-Mbit 64 K x 32 Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync SRAM Features Functional Description The CY7C1329H[1] SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by

CY7C1329H

Abstract: CY7C1329H-166AXC
Contextual Info: CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times

Contextual Info: fax id: 1080 CYPRESS 64K x 32 Synchronous-Pipelined Cache RAM PRELIMINARY sf Features Functional Description • Low 1.65 m W s ta n d b y p o w er (f=0, L ve rs io n ) • S u p p o rts 1 0 0 -M H z bus fo r P en tium and P ow erP C ™ o p e ratio n s w ith zero w a it states

toshiba tc 97101

Abstract: tc 97101 M7401 M73049 "256K x 16" SRAM PLCC M73002 M7206 M7-300 M72016 T 9722
Contextual Info: CYPRESS SEMICONDUCTOR CORPORATION PRODUCT RELIABILITY REPORT QUARTER 3, 1997 PERFORM PER THE REQUIREMENT OF 25-00008, RELIABILITY MONITOR PROGRAM SPECIFICATION Marc Hartranft QA Engineering Department Manager CYPRESS SEMICONDUCTOR CORPORATION PRODUCT RELIABILITY REPORT