QS8818 Search Results

AEB DP1

Contextual Info: QS88182 Q S88182 High-Speed CMOS Dual 4Kx18 Cache Tag SRAM Ô ADVANCE INFORMATION FEATURES/BENEFITS Dual 4Kx18 allows 2-way set associative cache tag MATCH lines per bank allow direct bank ÜE drive MATCH enable controls MATCH outputs for speed 20ns/25 ns/30 ns Taa Commercial

Contextual Info: QS88180, Q QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses QS88180 QS88160 FEATURES/BENEFITS • • • • Dual 4Kx18/16 allows 2-way set associative cache Byte enables for byte/Word read/write 20ns/25 ns/30ns/35 ns Taa Available in 52-pin PLCC

block diagram of 486

Contextual Info: QS88181 Q High-Speed CMOS 8Kx18 Burst Mode SRAM . « i l a , with Address Counter QS88181 ,I w bdM ,!;Aî TÏ,I OoIN Nf Fo OaR FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondary cache 1 clock initial access + 1 clock/word 40, 33, 25 MHz clock frequency

AEB DP1

Abstract: power bank 5v associative cache match
Contextual Info: QS88182 Q S88182 High-Speed CMOS Dual 4Kx18 Cache Tag SRAM Q ADVANCE IN F O R M A T IO N F E A T U R E S /B E N E F IT S Dual 4Kx18 allows 2-way set associative cache tag MATCH lines per bank allow direct bank Ü E drive MATCH enable controls MATCH outputs for speed

AEB DP1

Abstract: 0588 82385 A12A D815
Contextual Info: Q S88180, Q QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses QS88180 Q S 88160 Prelim inary FE A T U R E S /B E N E FIT S • • • • • Dual 4Kx18/16 allows 2-way set associative cache Byte enables for byte/word read/write 20ns/25 ns/30ns/35 ns Taa commercial

block diagram of 486

Abstract: sram with address counter
Contextual Info: QS88181 Q High-Speed CMOS_ o _ r _ _ _ _ _ _ 8Kx18 Burst Mode SRAM with Address Counter QS88181 « n \/A M rc ADVANCE INFORMATION FEATURES/BENEFITS • • • • 8Kx18with burst mode for secondarycache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency

Contextual Info: QS88180, ô QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses QS88180 QS88160 Preliminary FEATURES/BENEFITS • • • • • Dual 4Kx18/16 allows 2-way set associative cache Byte enables for byte/word read/write 20ns/25 ns/30ns/35 ns Taa commercial

A011 transistor

Contextual Info: QS88180, QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses Q 7 QS88180 Q S88160 Preliminary FEATURES/BENEFITS • • • • • Dual 4Kx18/16 allows 2-way set associative cache Byte enables 1or byte/word read/write 20ns/25 ns/30ns/35 ns Taa commercial

Contextual Info: QS88180, Q QS88160 High-Speed CMOS Dual 4Kx16/18 SRAM with Latched Addresses QS88180 QS88160 FEATURES/BENEFITS • Dual 4Kx18/16 allows 2-way set associative cache • Byte enables for byte/word read/write • 20ns/25 ns/30ns/35 ns Taa • Available in 52-pin PLCC

sram with address counter

Abstract: RISC and CISC COUNTER LOAD
Contextual Info: QS88181 Q High-Speed CMOS_ _ w _ r _ 8Kx18 Burst Mode SRAM with Address Counter Q S88181 a ni/ ADVANCE IN FO R M A TIO N F E A T U R E S /B E N E F IT S • • • • 8Kx18with burst mode for secondary cache 1 clock initial access +1 clock/word 40, 33, 25 MHz clock frequency

TAG 064

Abstract: power bank 5v S8818
Contextual Info: QS88182 Q High-Speed CMOS Dual 4Kx18 Cache Tag SRAM Q S88182 ADVANCE INFORMATION FEATURES/BENEFITS • • • • • • Dual 4Kx18 allows 2-way set associative cache tag MATCH lines per bank allow direct bank ÜE drive MATCH enable controls MATCH outputs for speed

82385

Abstract: TW 8816 OS8818 8818 c5t transistor NX18 QS8816 DPO/DSA70000B
Contextual Info: QUALITY SEMICONDUCTOR INC. High-Speed CMOS Dual 4KX16/18 SRAM with Latched Addresses Q X16 SRAM QS8816/7 x18 SRAM ^ I h c e in f o r m a t i o n FEATURES/BENEFITS Dual 4Kx18 allows 2-way set associative cache Latched and unlatched A12 versions 20ns/25 ns/35 ns Taa, 8 ns Toe