Q0042 Search Results

Contextual Info: POÜIEREX I N C 31E » • TETMbEl GGDMSSfi Z Q W E R E X 3 MIPRX KD421K15HB Powerex, Inc., Hlllls Street, Youngwood, Pennsylvania 15697 412 925-7272 Powerex Europe, S.A., 428 Avenue G, Durand, BP107,72003 Le Mans, France (43)41.14.14 f - l ï - 3!r High-Beta

Altera EPM5128

Abstract: K941 EPM5128 K1188 L883 Altera 48-macrocell application 74series
Contextual Info: EPM 5128 EPLD Figure 14. EPM5128 Package Pin-Out Diagrams Package outlines no t drawn to scale. See Tables 4 and 5 in this data sheet fo r pin-out information. Windows in ceramic packages only. . nn n nnn n nnnnnnnnnn I/O C I/O c 3 I'O 3 i/o I/o c I/o c □ I/O

M02S7S7

Contextual Info: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception • Schottky Clamped for High Performance

Contextual Info: S P SPT79 T IO 12-BIT, 10 MSPS, ECL, A/D CONVERTER SIGNAL PROCESSING TECHNOLOGIES FEATURES APPLICATIONS • • • • • • • • • • • • • • • • Monolithic 12-Bit 10 M SPS Converter 67 dB SNR @ 500 kHz Input On-Chip Track/Hold Bipolar ±2.0 V Analog Input

Q0042

Contextual Info: Types CGS, CG, CGR, CGO, CGH Dimensions and Size Charts • M allo r Y Case Code Chart Uninsulated Can_ _Inches . — A O O r o a « o E 3 R2C R2L R3C R3L R4C R4L R5C R5L U2C U2L U3C U3L U4C U4L U5C U5L V2C V2L V3C V3L V4C V4L V5C V5L W3C W3L W4C

HY514260BJC

Contextual Info: HY514260B Series •HYUNDAI 256K X 16-bit CMOS DRAM with 2CAS DESCRIPTION The HY514260B is the new generation and fast dynamic RAM organized 262,144 x 16-bit configuration employing advance submicron CMOS process technology and advanced circuit design techniques to achieve fast access

Contextual Info: S ta n d a rd P r o d u c t _w_ PMC I/ l ^ I PMC-Sierra, Inc. ISSUE 3 PM7375 LASAR-155 LOCAL A m SAR & PHYSICAL LAYER 1. F E A T U R E S • Single-chip Peripheral Component Interface PCI Bus Local ATM Network Interface using SONET/SDH framing at 155.52 or 51.84 Mbit/s and ATM

Contextual Info: 5SC » • ÛH3SbOS QÜ0MSS4 T ■ S I E 6 r NPN Silicon AF Transistors - 25C BCX 22 BCX 24 0 4 7 *5 ^ SIEMENS AKTIEN6ESELLSCHAF BCX 22, BCX 24, and BCX 94 are epitaxial NPN silicon planar transistors in TO 18 metal case 18 A 3 DIN 41876 . The collector is electrically connected to the case. These transistors

AAES

Abstract: V3061
Contextual Info: tì I . 2SC D • û23Sfc.0S GD0425Ô 7 H S I E â Z5C U*t258 PNP Silicon AF Transistors - BCX23 BCX 3 9 SIEMENS AKTIENGESELLSCHAF - — — =- -— BCX 2 3 and BCX 39 are epitaxial PNP silicon planar transistors in TO 18 metal case

EPLD JEDEC MAPPING

Contextual Info: XC7272A 72-Macrocell CMOS EPLD £ xilinx Preliminary Product Specifications Features The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic

686 ami bios

Abstract: ami bios 686 RF DELAY LINE 4.3GH A1m anode BZT 030 SARS 03 star delta FORWARD / REVERSE WIRING CONNECTION PX334 845 Mother board Diagram cops instrument display
Contextual Info: S TANDARD PRODUCT PMC-Sierra, Inc. ISSUE 3 P M 7 3 7 5 LASAR-155 LOCAL ATM SAR & PHYSICAL LA YER 1. FEA TU R ES • Single-chip Peripheral Component Interface PCI Bus Local ATM Network Interface using SONET/SDH framing at 155.52 or 51.84 Mbit/s and ATM Adaptation Layer 5 (AAL-5).

Q0051

Abstract: Q0032 Q0043 Q004
Contextual Info: Application Note Frequently Asked Questions on Development Tools and Products Fujitsu Mikroelektronik GmbH, Microcontroller Application Group History 2nd August 99 HLO Original version of master and database Note: This document is currently under development. This first version covers only a

Contextual Info: A p p l ic a t io n N ote A V A I L A B L E AN56 J ü s X20C16 16K e r 2K x 8 Bit High Speed AUTOSTORE NOVRAM FEATURES DESCRIPTION • Fast Access Time: 35ns, 45ns, 55ns • High Reliability — Endurance: 1,000,000 Nonvolatile Store Operations — Retention: 100 Years Minimum

467200

Contextual Info: IBM04181ARLAB IBM04361ARLAB Preliminary 32K X 36 & 64K X 18 SRAM Features • 32K x 36 or 64K x 18 Organizations • Latched Outputs • 0.5 Micron CMOS Technology • Asynchronous Output Enable and Power Down Inputs • Synchronous Register-Latch Mode of Opera­