PO44 Search Results

PO 168

Abstract: PO150C 420C PO150B PO406 PO450C
Contextual Info: Cut Charts PO SERIES PO150C / PO150B Page: 1 of 1 Date: 03/08 PO440C Operating Freq. Inches 124.5 440 MHz 10 1/4 26.0 47 1/2 120.7 445 MHz 9 3/4 24.8 152 MHz 46 116.8 450 MHz 9 1/8 23.2 156 MHz 44 1/4 112.4 455 MHz 8 3/4 22.2 160 MHz 42 1/2 108.0 460 MHz 8 3/8

circuit diagram of Tri-State Buffer using CMOS

Abstract: verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart
Contextual Info: Features • 0.5 µm Drawn Gate Length 0.45 µm Leff Sea-of-Gates Architecture with • • • • • Triple-level Metal Embedded E2 Memory up to 256 Kb 3.3V Operation with 5.0V Tolerant Input and Output Buffers High-speed, 200 ps Gate Delay, 2-input NAND, FO = 2 Nominal

ATL35

Abstract: CL11 PO22 PO33 PO44 PO55 ATL35/208
Contextual Info: ATL35 I/O Buffer Cell Library-1.0-12/97 ATL35 0.35µ I/O Buffer Cell Library I/O Buffer Naming Convention . 8-2 I/O Site: Pad and Sub-Sections . 8-2

AOI222

Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter
Contextual Info: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:

AVR 8515 microcontroller

Abstract: FPGA AMI coding decoding tri state AOI222 AOI2223 AOI2223H AOI222H ATL35 0.35-um CMOS standard cell library inverter
Contextual Info: Features • System Level Integration Technology • 0.35 µm Geometry in Triple-level Metal • I/O Interfaces; CMOS, LVTTL, LVDS, PCI, USB – Output Currents up to 20 mA, 5V Tolerant I/O • Embedded Flash Memory with Capacities of 1Mbit, 2Mbit or 4Mbit

tristate buffer

Abstract: smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E
Contextual Info: Features • High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal • Up to 1.198M Used Gates and 512 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Space Quality Grades • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries when Tested to

54175

Abstract: PO11V5 16889 49035 56374 28548 58128 13.562 93408 atmel 246
Contextual Info: ERRATA SHEET DATE: April 2009 TO: Aerospace customers SUBJECT: 5V COMPLIANT BUFFERS WITH CORE POWERED AT 2.5V A 5V compliant buffer is a buffer powered by a 5V supply which is able to tolerate with negligible leakage current and without any reliability problems 5V signals (input buffer and pullup/pull-down) or drive 5V signals on its output (output buffer).

AT 2005A

Abstract: L33 TRANSISTOR ATMEl 837 ARM CORE 1825 verilog code for UART with BIST capability 8 bit risc microprocessor using vhdl L33v verilog code for 32 bit risc processor 2005A-ASIC-06 MIPS64 5kf
Contextual Info: Features • • • • • Available in Gate Array, Embedded Array or Standard Cell High-speed, 75 ps Gate Delay, 2-input NAND, FO = 2 nominal Up to 13.7 Million Used Gates and 1516 Pins 0.18µ Geometry in up to Six-level Metal System-level Integration Technology

1F00H-1FFFH

Abstract: TMS370C777A "TMS370 Family Data Manual" SE370C777A texas instruments ttl manual TMS370 SPNS014
Contextual Info: TMS370Cx7x 8-BIT MICROCONTROLLER S PN S034B-SEPTEM BER 1 9 9 5 - REVISED MARCH 1996 CMOS/EEPROM/EPROM Technologies on a Single Device - Mask-ROM Devices for High-Volume Production - One-Time-Programmable OTP EPROM Devices for Low-Volume Production - Reprogrammable EPROM Devices for

atmel 216

Abstract: ECL IC NAND CQFP 256 PIN actel Atmel 642 PO22 tri state ATL35 atmel 334 20PCI atmel h 952
Contextual Info: Features • High-speed - 150 ps Gate Delay - 2-input NAND, FO = 2 nominal • Up to 2.7 Million Used Gates and 976 Pins • System Level Integration Technology – Cores: ARM7TDMI and AVR RISC Microcontrollers, OakDSP™ and LodeDSPCores™, 10T/100 Ethernet MAC, USB and PCI Cores

PO77

Contextual Info: ATL25 I/O Buffer Cell Library - Preliminary - 1.1 - 09/99 ATL25 0.25µ I/O Buffer Cell Library Preliminary I/O Buffer Naming Convention . 8-2 I/O Site: Pad and Sub-sections. 8-2

TI Marking P272

Abstract: p135L mip283 L5106 ALI 3101 C I-CUBE iq P109t transistor P239 416L CA3125
Contextual Info: •Pt I - C u b IQX Family Data Sheet e m F eatures D e s c r ip t io n • SRAM-based, in-system programmable The IQX family of SRAM-based bit-oriented switching devices is • Switch Matrix manufactured using a 0.6nm CMOS process. These devices offer clock speeds of up to 133 MHz and pin-to-pin delay as low

Contextual Info: PO11 ATL25 CMOS Gate Array cell data sheets 4.0 Description: Tristate output buffer, 2mA drive. Characterization: 25C, 3.3v, Nominal Process Cell area sites : 0.0 Pin caps(pF): AO=0.060, E0=0.060 Typical delay times (slope in ns/pF; intercept in ns; input transition = 0.600ns):

PO77F

Abstract: PO55F 090569 PO55V 24236 PO11F 328-529 po11s PX2L PO22
Contextual Info: ATL35 I/O Buffer Cell Library-1.4-09/99 ATL35 0.35µ I/O Buffer Cell Library I/O Buffer Naming Convention . 8-2 I/O Site: Pad and Sub-Sections . 8-2

PO88

Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5
Contextual Info: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:

Contextual Info: RT9170 1. 1.1 Intelligent T1 Controller INTRODUCTION 1.2 SUMMARY * The Rockwell RT9170 Intelligent T1 Controller is a micro­ processor MPU controlled device which implements a T1 interlace between the multiplexed digital DS1 signal and the PCM highway of digital voice and data system equip­

TEMIC PLD

Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099
Contextual Info: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The

uPD447-2

Contextual Info: N E C M i c r o c o m p u t e r s , I n c . ^ p d u 7 ^ /x PD447-1 H PD447-2 2048 x 8 BIT STATIC CMOS RAM D E S C R IP T IO N The /jPD447 is a high speed, low power, 2048 word by 8 bit static CMOS RAM fabricated using an advanced silicon gate CMOS technology. A unique circuitry tech­

SMCS116

Abstract: AT7910 SMCS116SpW SMCS332SpW SpaceWire SpaceWire cable AT7910E ECSS-E50 Am-263 E48-series
Contextual Info: SpW-10X SpaceWire Router User Manual Ref.: UoD_SpW-10X_ UserManual Issue: 3.4 Date: 11th July 2008 SpW-10X SpaceWire Router User Manual Ref: UoD_SpW-10X_UserManual Atmel Part No.: AT7910E Document Revision: Issue 3.4 Date: 11th July 2008 Prepared by - Chris McClements, University of Dundee

Transistor Equivalent list po55

Abstract: atmel 938 on digital code lock using vhdl mini pr credence tester 2042B atmel 532 atmel 422 bsu 479 atmel 424 2042B-ASIC
Contextual Info: ATL25 Series . Design Manual Table of Contents Section 1 ATL25 Series ASIC. 1-1 1.1 1.2

I-CUBE

Abstract: 2P034 P001 pb416 PO88 TPA 4863 A18K tq52 P046 P009
Contextual Info: & l •Cube IQ Family Data Sheet Update IQ96, IQ64B, IQ48, IQ32B Features Description • • These additional members in the IQ previously called FPID family are based on 0.6|im CMOS Process. • • • • • 32, 48, 64 and 96 I/O Ports SRAM-based Programming for In-system

Transistor Equivalent list po55

Abstract: Structure of D flip-flop DFFSR tristate buffer sis 968 PO-44Z PRU11 AC/DC drive nec 78054 PO22 tristate buffer cmos
Contextual Info: Features • High Speed - 180 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.198 M Used Gates and 512 Pads with 3.3 V, 3V and 2.5V libraries when tested to space quality grades • Up to 1.6M Used Gates and 596 Pads with 3.3 V, 3V and 2.5V libraries when tested to

spw -136

Abstract: SMCS116
Contextual Info: SpW-10X SpaceWire Router User Manual Ref.: UoD_SpW-10X_ UserManual Issue: 3.4 Date: 11th July 2008 SpW-10X SpaceWire Router User Manual Ref: UoD_SpW-10X_UserManual Atmel Part No.: AT7910E Document Revision: Issue 3.4 Date: 11th July 2008 Prepared by - Chris McClements, University of Dundee

mip283

Abstract: P124d ST P239 p037 ke EL B17 A017 I-CUBE ior p135 p005 ab 48 tag 91 P106t TI Marking P272
Contextual Info: •Pt I - C u b IQX Family Data Sheet e m F eatures D e s c r ip t io n • SRAM-based, in-system programmable The IQX family of SRAM-based bit-oriented switching devices is • Switch Matrix manufactured using a 0.6nm CMOS process. These devices offer clock speeds of up to 133 MHz and pin-to-pin delay as low