MH1242 Search Results

ATMEL 634

Abstract: ambit rev 4 LSI CMOS GATE ARRAY PO11V5 MH1099 MH1242 705uA
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TPRAM; Gate Level or Embedded

AOI222

Abstract: AOI2223 AOI222H MH1099 MH1242 0.35-um CMOS standard cell library inverter
Contextual Info: Features • High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries • System Level Integration Technology Cores on Request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:

tristate buffer

Abstract: smd transistor AO HEX TO DECIMAL tristate buffer cmos A101 A201 MH1099E MH1156E PO11F MH1332E
Contextual Info: Features • High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal • Up to 1.198M Used Gates and 512 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Space Quality Grades • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries when Tested to

DIGITAL IC TESTER report for project

Abstract: atmel 504 IO33 ATC18RHA 4261C virage IO33
Contextual Info: Features • Comprehensive Library of Standard Logic and I/O Cells • ATC18RHA Core and IO18 pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main • • • • • • • • • • • • • • Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V Environments

ta 8268

Abstract: qml-38535 4090 F 01B01 marking code 33916 MH1242ER smd code MH1
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Add device type 09 – 32 and appendix A. - phn 02-02-11 Thomas M. Hess B Add Case outline U and T. Editorial changes throughout. - phn 03-06-03 Thomas M. Hess C Change maximum supply voltage range from 3.6 V to 4.0 V and from 5.5 V to

MH1099

Abstract: MH1242 PO11V5 4138G
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E AMI 1108
Contextual Info: Features • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E atmel 838 atmel edac dsp radiation hard
Contextual Info: Features • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

DIGITAL IC TESTER report for project

Abstract: ATMEL 644 IO33 4261F ATC18RHA Genesys Logic MQFP-F196 5962-06B02 atmel 216 4261b
Contextual Info: Features • • • • • • • • • • • • • • • • Comprehensive Library of Standard Logic and I/O Cells ATC18RHA Core pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V and 2.5 +/- 0.25V Environments

DIGITAL IC TESTER report for project

Abstract: MCGA349 PL33RXZ atmel 504 ATMEL 644 ATC18RHA 5962-06B02 MQFP-T352 IO33 mcga
Contextual Info: Features • • • • • • • • • • • • • • • • Comprehensive Library of Standard Logic and I/O Cells ATC18RHA Core pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V and 2.5 +/- 0.25V Environments

ATMEL 634

Abstract: ambit rev 4 C 828 dual mcga SRAM edac A101 A201 MH1099E MH1156E MH1242E
Contextual Info: Features • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

PO88

Abstract: ttl buffer AOI222 AOI2223 AOI2223H AOI222H MH1099 MH1242 PRD21 PRD29V5
Contextual Info: Features • High Speed - 170 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.6 Million Used Gates and 596 pads, with 3.3V, 3V, and 2.5V libraries • System Level Integration Technology Cores on request: SRAM and TRAM (Gate Level or Embedded) • I/O Interfaces:

Contextual Info: Features • • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

TEMIC PLD

Abstract: PRU10 PRD8 buffer 8x Structure of D flip-flop DFFSR AOI222 AOI2223 AOI2223H AOI222H MH1099
Contextual Info: MH1 1.6 Million gates Sea of Gates / Embedded Arrays 1. Description The MH1 Series Gate Array and Embedded Array families from TEMIC are fabricated in a 0.35µ CMOS process, with up to 3 levels of metal. This family features arrays with up to 1.6 million routable gates and 600 pins. The

ATMEL 634

Abstract: MH1099 MH1242 PO11V5 dual lvds vhdl
Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

Contextual Info: Features • • • • • Up to 1.6 Million Used Gates and 596 Pads, with 3.3V, 3V, and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 Nominal System Level Integration Technology Cores on Request SRAM and TRAM (Gate Level or Embedded)

A101

Abstract: A201 MH1099E MH1156E MH1242E MH1332E HEX TO DECIMAL ATMEL 220 dsp radiation hard
Contextual Info: Features • • • • • • • • • • • • Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries High Speed - 170 ps Gate Delay - 2 Input NAND, FO = 2 nominal System Level Integration Technology Cores on Request Memories: SRAM and TPRAM, Gate Level or Embedded, with EDAC

Atmel 544

Abstract: atmel 504 atmel 404 MQFPT352 MLGA625 725m 5962-06B02 atmel h 404 MH1242E 404D
Contextual Info: Features • • • • • • • • • • • • • • • • • Comprehensive Library of Standard Logic and I/O Cells Up to 6.5 usable Mgates equivalent NAND2 Operating voltage 1.8V for core and 3.3V or 2.5V for I/O’s Memory Cells Compiled or synthesized to the Requirements of the Design

MH1RT

Abstract: 65609E AT56K sn17
Contextual Info: MH1RT QualPack Qualification Package MH1RT Sea of Gates Radiation Tolerant 0.35 µm CMOS MH1RT Sea of Gates 0.35 µm CMOS for Space Environment QualPack Rev.2 – Jan. 2002 1 MH1RT QualPack 1. Table of Contents 1. Table of Contents . 2

Transistor Equivalent list po55

Abstract: Structure of D flip-flop DFFSR tristate buffer sis 968 PO-44Z PRU11 AC/DC drive nec 78054 PO22 tristate buffer cmos
Contextual Info: Features • High Speed - 180 ps Gate Delay - 2 input NAND, FO=2 nominal • Up to 1.198 M Used Gates and 512 Pads with 3.3 V, 3V and 2.5V libraries when tested to space quality grades • Up to 1.6M Used Gates and 596 Pads with 3.3 V, 3V and 2.5V libraries when tested to

5962-01B01

Abstract: perfo 124 373 01B01 vhdl code 4794 qml-38535 3629 BP 4090 Datasheet ci 4009 5962-01B0115V9A 5962-01B0111V
Contextual Info: REVISIONS LTR DESCRIPTION A DATE YR-MO-DA APPROVED 02-02-11 Thoma M. Hess Add device type 09 – 32 and appendix A. - phn REV A SHEET 55 REV A A A A A A A A A A A A A A A A A A A A SHEET 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 REV A A

atmel13

Abstract: 0.18-um CMOS technology characteristics DIGITAL IC TESTER report for project ATMEL 644 IO33 IC Ensemble ATC18RHA IBIS model Genibis Atmel IO33 ATC18RHA atmel 336
Contextual Info: Features • Comprehensive Library of Standard Logic and I/O Cells • ATC18RHA Core and IO18 pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main • • • • • • • • • • • • Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V Environments

qml-38535

Abstract: 6227 4090 Datasheet ci 4009 Y-351 vhdl code 4794 smd code MH1
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Add device type 09 – 32 and appendix A. - phn 02-02-11 Thomas M. Hess B Add Case outline U and T. Editorial changes throughout. - phn 03-06-03 Thomas M. Hess C Change maximum supply voltage range from 3.6 V to 4.0 V and from 5.5 V to