PLB 405 Search Results

IPIF

Contextual Info: PLB Ethernet Media Access Controller PLB_EMAC (v1.01a) DS474 August 19, 2004 Product Specification Introduction LogiCORE Facts The PLB Ethernet 10/100 Mbs Media Access Controller (PLB_EMAC) with interface to the Processor Local Bus (PLB) has been designed incorporating the applicable features described in IEEE Std. 802.3 MII interface specification. The IEEE Std. 802.3 MII interface specification is

RGMII to SGMII bridge

Abstract: 0x010203040506 P100 P101 P102 P103 P104 P105 P106 P107
Contextual Info: PLB TEMAC v2.00a DS489 June 30, 2005 Product Specification Introduction LogiCORE Facts This document provides the design specification for the PLB_TEMAC (PLB interfaced Tri-mode Ethernet Media Access Controller). Tri-mode indicates that this core may

plb 405

Abstract: powerpc 405
Contextual Info: Application Note Preliminary Attaching PowerPC 405 Core to PLB Crossbar Arbiter This application note is intended for users of the 128-bit PLB Crossbar Arbiter Core who need to attach more than 8 masters, but have slaves that are not designed to support more than 8 masters.

PLB DDR2 with PLB Central DMA

Abstract: DDR2 SDRAM ECC and Application Note PLB DDR2 with OPB Central DMA DS472 ML410 XAPP935 plb 405
Contextual Info: Application Note: Embedded Processing R XAPP935 v1.1 June 7, 2007 Abstract Reference System: PLB DDR2 with OPB Central DMA Author: James Lucero This reference system demonstrates the functionality of the Processor Local Bus (PLB) Double Data Rate 2 (DDR2) Synchronous DRAM (SDRAM) memory controller in a PowerPC 405

XILINX ipic

Abstract: full bridge IPIF asynchronous PAR64 PCI32 REQ64 SG28c Virtex-4 User Guide
Contextual Info: PLB PCI Full Bridge v1.00a DS508 March 21, 2006 Product Specification Introduction LogiCORE Facts Supported Device Family Virtex™-II Pro, Virtex-4 plb_pci Resources Used Virtex-IIP Min Max 49 50 I/O (PLB-related) 397 433 LUTs 3350 3870 2570 2970 8 8

Marvell 88e111

Abstract: 88e111 ML405 Marvell 88e111 driver Marvell PHY Xilinx virtex 1000BASE-X DML300 PPC405 XAPP941 Tcp1323Opts
Contextual Info: Application Note: Embedded Processing R XAPP941 v1.1 June 15, 2007 Reference System: PLB Tri-Mode Ethernet MAC Author: Robert McGee and Norbert Melnikov Abstract This application note describes a reference system illustrating how to build an embedded PowerPC system using the Virtex™-4 PLB Tri-Mode Ethernet Media Access Controller

XC6SLX16-2CSG324

Abstract: asynchronous fifo vhdl 0xE000000F DS571 uart 19200 ise one stop bit XC6SLX16-2 uart vhdl fpga XILINX FIFO UART baud rate generator vhdl xc3s250e-4-ft256
Contextual Info: XPS UART Lite v1.01a DS571 December 2, 2009 Product Specification Introduction LogiCORE IP Facts The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides the controller interface for

IBM processor

Abstract: PPC405 XILINX ipic 2VP7FF896-6 fpga frame buffer vhdl examples
Contextual Info: RapidIO Processor Buffer DS241 v1.0 December 20, 2002 Interface Specification Introduction LogiCORE Facts The RapidIO Processor Buffer provides an interface between the Xilinx Processor Local Bus—Intellectual Property Interface (PLB-IPIF) and the Xilinx 8-bit LP/LVDS

XAPP809

Abstract: DS460 Gemac ml300 ucf
Contextual Info: Application Note: Embedded Processing R XAPP809 v1.2 June 5, 2007 Reference System: PLB Gigabit Ethernet MAC with a SerDes Interface Author: Norbert Melnikov Summary This application note describes a reference system which illustrates how to build an embedded

ALi M1535D

Abstract: vhdl code for vending machine XC4VFX60 PLB DDR2 with OPB Central DMA XCF32PFSG48C PLB CONNECTOR m1535d manual ALi M1535D ALI usb PDC202
Contextual Info: Application Note: Embedded Processing Reference System: PLB PCI Using the ML410 Embedded Development Platform R Author: Lester Sanders XAPP945 v1.1 February 8, 2008 Summary This application note describes how to build a reference system for the Processor Local Bus

PPC405EX-SSC600T

Abstract: AMCC errata PPC405EX 405EX SPI NAND FLASH "ESP" PPC405EX-NSD600T AMCC PPC405EX
Contextual Info: Part Number 405EX Revision 1.23 - January 28, 2009 405EX Data Sheet PowerPC 405EX Embedded Processor Features • AMCC PowerPC 405 32-bit RISC processor core operating from 333MHz to 600MHz including 16KB I- and D-caches with parity checking • 128-bit processor local bus PLB operating up to

SPI NAND FLASH

Abstract: PPC405EX amcc 460EX EIP94 640KB
Contextual Info: Part Number 405EX Revision 1.14 - January 4, 2008 405EX Preliminary Data Sheet PowerPC 405EX Embedded Processor Features • AMCC PowerPC 405 32-bit RISC processor core operating from 333MHz to 600MHz including 16KB I- and D-caches with parity checking • On-chip 128-bit processor local bus PLB

AMCC ppc405

Contextual Info: Part Number 405EXr Revision 1.09 - May 2, 2008 405EXr Preliminary Data Sheet PowerPC 405EXr Embedded Processor Features • AMCC PowerPC 405 32-bit RISC processor core operating from 333MHz to 533MHz including 16KB I- and D-caches with parity checking • On-chip 128-bit processor local bus PLB

XC5VLX50-FF676

Abstract: XC4VFX12-FF668-10 xc5vlx50-ff676-1 XC6VLX130TFF1156 XC3S700A VIRTEX-5 DDR2 controller DS570 AT45DB161D M25P16 PLBV46
Contextual Info: XPS Serial Peripheral Interface SPI (v2.01b) DS570 September 16, 2009 Product Specification 0 0 Introduction LogiCORE Facts The XPS Serial Peripheral Interface (SPI) connects to the PLB V4.6 (Processor Local Bus with Xilinx simplifications) and provides a serial interface to SPI

SPI NAND FLASH

Abstract: 073f
Contextual Info: Part Number 405EX Revision 1.20 - May 2, 2008 405EX Preliminary Data Sheet PowerPC 405EX Embedded Processor Features • AMCC PowerPC 405 32-bit RISC processor core operating from 333MHz to 600MHz including 16KB I- and D-caches with parity checking • 128-bit processor local bus PLB operating up to

405EX

Abstract: uart 16750 "ESP" PPC405EX-SSC600 epbg
Contextual Info: Part Number 405EX Revision 1.23 - January 28, 2009 405EX Data Sheet PowerPC 405EX Embedded Processor Features • AMCC PowerPC 405 32-bit RISC processor core operating from 333MHz to 600MHz including 16KB I- and D-caches with parity checking • 128-bit processor local bus PLB operating up to

spi nand

Abstract: AMCC DTLs SPI NAND FLASH SHA-256 asic EIP94
Contextual Info: Part Number 405EX Revision 1.19 - April 3, 2008 405EX Preliminary Data Sheet PowerPC 405EX Embedded Processor Features • AMCC PowerPC 405 32-bit RISC processor core operating from 333MHz to 600MHz including 16KB I- and D-caches with parity checking • On-chip 128-bit processor local bus PLB

Contextual Info: LogiCORE IP XPS Universal Serial Bus 2.0 Device v7.01a DS639 October 16, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx Universal Serial Bus 2.0 High Speed Device with Processor Local Bus (PLB) v4.6 enables Universal Serial Bus (USB) connectivity to a user design with a

RGMII constraints

Abstract: TEMAC free source code for cdma transceiver using vhdl 7206 cisco power requirement 7206 cisco GMII VLAN Tag RGMII RGMII phy DS537 LocalLink
Contextual Info: XPS LL TEMAC v2.03a DS537 December 2, 2009 Product Specification Introduction LogiCORE Facts This document provides the design specification for the XPS_LL_TEMAC soft Ethernet core. This core provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the

XILINX ipic

Abstract: PLBv46 MPLB north bridge PCI32 V102-A IPIF asynchronous
Contextual Info: PLBV46 PCI Full Bridge v1.00a DS616 Aug 24, 2007 Product Specification Introduction LogiCORE Facts The PLBV46 PCI Full Bridge design provides full bridge functionality between the Xilinx PLB and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI) bus. The bridge is referred to as the

PPC405

Abstract: 4926N XAPP640 4021N EICC405CRITINPUTIRQ 4021-N 9022N
Contextual Info: Application Note: Virtex-II Pro Family R Timing Constraints for Virtex-II Pro Designs XAPP640 v1.1 January 16, 2003 Summary This application note discusses the usage of timing constraints in a Virtex-II Pro design with the PowerPC™ 405 (PPC405) processor. The interaction of the timing constraints with the

IBM25PPC405EP Application

Abstract: PPC4 PPC405EP PPC405D4V6 AMCC ppc405ep 405EP PPC405 PCI24 PCI25 erratum 405 amcc
Contextual Info: 405EP Errata Device Errata Rev 1.1 IBM25PPC405EP-3GBxxxCx February 8, 2008 This document contains errata and design notes that affect designs using the PPC405EP Rev 1.1 (PVR 0x51210950). Each erratum includes an overview, a description of the system impact and a description of possible

AMCC DATE CODE

Abstract: PPC405GPr PPC405 AMCC ppc405 plb pci bridge deadlock AMCC errata amcc date code format
Contextual Info: Part Number 405GPr Revision 1.00 – February 12, 2008 405GPr Errata PPC405GPr Revision 1.1 Embedded Processor This document contains errata and design notes that affect designs using the PPC405GPr Revision 1.1. Each erratum includes an overview, a description of the system impact and a description of possible work-around s .

vhdl code for watchdog timer of ATM

Abstract: powerpc 405 vhdl code 64 bit FPU Digital Core Design USB modulo basics GPS clock code using VHDL RISCwatch Trace "Overflow detection" IAC3 64 bit MAC code verilog
Contextual Info: The PowerPC 405TM Core IBM Microelectronics Division Research Triangle Park, NC 27709 11/2/98 Overview The PowerPC 405 CPU Core is a new addition to the 32-bit RISC PowerPC Embedded Processor family. The 405 Core possesses all of the qualities necessary to make system-on-a-chip designs a reality. This