LOCALLINK Search Results

vhdl code CRC

Abstract: C704DD7B SP006 4C11DB7 CRC calculation XAPP209 XAPP562 d9862f10 CRC Series C0010203
Contextual Info: Application Note: Virtex Series and Virtex-II Family Configurable LocalLink CRC Reference Design R Author: Nanditha Jayarajan XAPP562 v1.1.1 April 20, 2007 Summary The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and

XAPP691

Abstract: LocalLink XAPP258 10939 RAM32X1D vhdl code CRC 32 RAM64X1D XAPP261 SP006 xilinx logicore fifo generator 6.2
Contextual Info: Application Note: Virtex-II and Virtex-II Pro Families R Parameterizable LocalLink FIFO Author: Wen Ying Wei, Dai Huang XAPP691 v1.0.1 May 10, 2007 Summary This application note describes the implementation of a parameterizable LocalLink FIFO, which is a First-In-First-Out memory queue with LocalLink interfaces on both sides. The LocalLink

vhdl code CRC

Abstract: vhdl code CRC 32 verilog code 3 bit CRC SP006 CRC64 polynomial CRC64 verilog code for digital calculator LocalLink verilog code for fibre channel vhdl code CRC32
Contextual Info: Virtex-5 CRC Wizard v1.2 DS589 October 10, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Cyclic Redundancy Check CRC Wizard provides a LocalLink wrapper for the CRC hard macro available in the Virtex™-5 LXT and SXT devices. The CRC Wizard can be customized to suit a wide

X1129

Abstract: linux26 ML507 PPC440 PPC440MC UART16550 XAPP1126 XAPP1129 xps serial peripheral interface 0x40400000
Contextual Info: Application Note: Embedded Processing R XAPP1129 v1.0 May 5, 2009 Abstract Integrating an EDK Custom Peripheral with a LocalLink Interface into Linux Author: Brian Hill This application note discusses the usage of a Local Link DMA peripheral with the Linux

DS504

Abstract: LocalLink
Contextual Info: SPI-3 Link Layer v5.1 DS504 August 8, 2007 Product Specification Introduction LogiCORE Facts The Xilinx LogiCORE SPI-3 Link Layer core provides a complete, pre-engineered solution that is fully compatible with the OIF-SPI3-01.0 System Packet Interface Level-3 standard. Implementation Agreement. This

verilog code for fibre channel

Abstract: DS518 RXRECCLK PPC405 xilinx 9.1i verilog code fc 2 vhdl code for frame synchronization xilinx logicore fifo generator vhdl code for loop verilog code for frame synchronization
Contextual Info: Fibre Channel Arbitrated Loop v2.2 DS518 August 8, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Fibre Channel Arbitrated Loop FC-AL core provides a flexible, fully verified solution for use in any FC-AL port design. The core handles all link initialization and loop arbitration functions and includes credit

XC3S500E

Abstract: reliability report of nxp PX1011A PX1011A-EL1 DO-DI-PCIEXP "network interface cards"
Contextual Info: 11 Endpoint PIPE v1.7 for PCI Express DS321 May 17, 2007 Product Specification Introduction LogiCORE Facts The Endpoint PIPE PHY Interface for PCI Express 1-lane core is a high-bandwidth scalable and reliable serial interconnect intellectual property building block

vhdl source code for i2c optic

Abstract: DS543 microblaze locallink
Contextual Info: MOST Network Interface Controller v1.2 DS543 August 8, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Media Oriented Systems Transport Network Interface Controller MOST NIC core is a complete controller designed to the MOST Specification

8e1111

Abstract: Marvell PHY 88E1111 ml505 Marvell PHY 88E1111 Datasheet microblaze ethernet ML505 ML507 sgmii 88E1111 Marvell PHY 88E1111 Xilinx XAPP957 88E1111 and SFP applications
Contextual Info: Application Note: Virtex-5 Embedded Tri-Mode Ethernet Core R Virtex-5 Embedded Tri-Mode Ethernet MAC Hardware Demonstration Platform XAPP957 v1.1 October 8, 2008 Summary This application note describes a system using the Virtex -5 Embedded Tri-Mode Ethernet

MP21608S221A

Abstract: UG198 FERRITE-220 GTX tile oversampling recovered clock ROSENBERGER verilog code for linear interpolation filter aurora GTX BLM15HB221SN1 gearbox rev maxim DVB
Contextual Info: Virtex-5 FPGA RocketIO GTX Transceiver User Guide UG198 v2.1 November 17, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

ug196

Abstract: johnson tiles GTX tile oversampling recovered clock XC5VLX30T-FF323 aurora GTX ROSENBERGER XC5VSX50TFF665 2F-15 UCF virtex-4 BLM15HB221SN1
Contextual Info: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.0 June 10, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

jesd79f

Abstract: UG388 MT41J256M8xx-187E 8 XC6SLX9 MT41J256M8xx-187E ddr3 ram slot pin detail MT41J64M16xx-187E micron DDR3 pcb layout MT41K128M8 Spartan-6 LX45
Contextual Info: Spartan-6 FPGA Memory Controller User Guide UG388 v2.3 August 9, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

XC4VLX15-FF668

Abstract: axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan
Contextual Info: LogiCORE IP FIFO Generator v8.3 DS317 October 19, 2011 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO

virtex-6 ML605 user guide

Abstract: UG353 vhdl code 8 bit LFSR ML605 UCF FILE virtex 5 fpga utilization simple 32 bit LFSR using verilog 65Gbps SP006 virtex-5 ML605 user guide aurora GTX
Contextual Info: LogiCORE IP Aurora 8B/10B v5.3 DS637 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex -5 LXT, SXT, FXT, and TXT

Contextual Info: LogiCORE IP Multi-Port Memory Controller v6.06.a DS643 February 22, 2013 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Multi-Port Memory Controller (MPMC) is a fully parameterizable memory controller that supports SDRAM/DDR/DDR2/DDR3/LPDDR

picoblaze

Abstract: microblaze ethernet microblaze ethernet lite microblaze Embedded Processing microblaze locallink SPARTAN-3 XC3S400 uclinux xc3s100 XAPP477
Contextual Info: Application Note: Spartan-3 FPGA Family R Embedded Processing and Control Solutions for Spartan-3 FPGAs XAPP477 v1.0.1 August 11, 2003 Introduction In a variety of applications, an embedded processor or controller is key to system flexibility, maintainability, and low cost. Spartan-3 FPGAs support two powerful yet flexible Field

XAPP477

Abstract: picoblaze Xilinx Parallel Cable IV spartan-3 XC3S400 uart microblaze ethernet lite microblaze SPARTAN 6 peripherals XC3S400 FPGAs Embedded Processing xilinx spartan xc3s400
Contextual Info: Application Note: Spartan-3 FPGA Family R Embedded Processing and Control Solutions for Spartan-3 FPGAs XAPP477 v1.0.1 August 11, 2003 Introduction In a variety of applications, an embedded processor or controller is key to system flexibility, maintainability, and low cost. Spartan-3 FPGAs support two powerful yet flexible Field

UG196

Abstract: MP21608S221A xc5vlx30t-ff323 XC5VLX155T-FF1738 XC5VSX50TFF665 direct sequence spread spectrum virtex-5 FERRITE-220 FF1136 XC5VLX30T-FF665 XC5VLX110T-FF1738
Contextual Info: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.1 December 3, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

vhdl code for DES algorithm

Abstract: XAPP921c FLOATING POINT PROCESSOR TMSC6000 pulse compression radar fir filter matlab code LMS adaptive filter simulink model verilog code for lms adaptive equalizer for audio LMS simulink 3SD1800A XILINX vhdl code REED SOLOMON encoder decoder fir filter with lms algorithm in vhdl code
Contextual Info: XtremeDSP Solutions Selection Guide June 2008 Introduction Contents DSP System Solutions.4 DSP Devices.17 Development Tools.25 Complementary Solutions.33 Resources.35

manual SPARTAN-3 XC3S400 evaluation kit

Abstract: hcl l21 usb power supply circuit diagram verilog code for Modified Booth algorithm vhdl code for lcd of spartan3E UG331 TT 2222 Horizontal Output Transistor pins out dia verilog for 8 point fft using FPGA spartan3 vhdl code for ldpc decoder types of multipliers ge fanuc cpu 331
Contextual Info: Spartan-3 Generation FPGA User Guide Extended Spartan-3A, Spartan-3E, and Spartan-3 FPGA Families UG331 v1.7 August 19, 2010 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development

XILINX ipic

Abstract: full bridge IPIF asynchronous PAR64 PCI32 REQ64 SG28c Virtex-4 User Guide
Contextual Info: PLB PCI Full Bridge v1.00a DS508 March 21, 2006 Product Specification Introduction LogiCORE Facts Supported Device Family Virtex™-II Pro, Virtex-4 plb_pci Resources Used Virtex-IIP Min Max 49 50 I/O (PLB-related) 397 433 LUTs 3350 3870 2570 2970 8 8

ML421

Abstract: 2310 fx ML320 ML423 ML325 sp002 DS083 DS112 ML321 ML323
Contextual Info: Aurora v3.0 DS128 September 19, 2008 Product Specification Introduction LogiCORE IP Facts The LogiCORE IP Aurora core implements the Aurora protocol on Virtex -II Pro and Virtex-4 FX FPGAs. The core can use up to 20 Virtex-II Pro or 24 Virtex-4 FPGA RocketIO™ multi-gigabit transceivers

XC6SLX45T-3FGG484C

Abstract: XC6SLX45T-3FGG484 sp605 XAPP492 xilinx mig user interface design SPARTAN-6 GTP XC6SLX45T-3F SFP MCB RAMB16BWERs xilinx DDR3 controller user interface
Contextual Info: Application Note: Spartan-6 Family Extending the Spartan-6 FPGA Connectivity TRD PCIe-DMA-DDR3-GbE to Support the Aurora 8B/10B Serial Protocol XAPP492 (v1.0) June 23, 2010 Summary Authors: Vasu Devunuri and Sunita Jain Targeted Reference Designs (TRDs) provide Xilinx designers with turn-key platforms to create

vhdl code for ethernet mac spartan 3

Abstract: TEMAC bench 2800 LocalLink sgmii fpga datasheets 1000BASE-X 1000X XAPP691 RGMII constraints verilog code for MII phy interface
Contextual Info: Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v4.7 Getting Started Guide UG240 April 24, 2009 R R Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You