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    onsemi FDS6375

    MOSFET P-CH 20V 8A 8SOIC
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    DigiKey () FDS6375 Cut Tape 8,160 1
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    Mouser Electronics FDS6375 18,438
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    Newark () FDS6375 Cut Tape 7,495 5
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    New Advantage Corporation FDS6375 102,500 1
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    Fairchild Semiconductor Corporation FDS6375

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    Bristol Electronics () FDS6375 14,277 6
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    Component Electronics, Inc FDS6375 291
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    Fairchild Semiconductor Corporation FDS6375-NL

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    Win Source Electronics FDS6375-NL 7,800
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    Fairchild Semiconductor Corporation FDS6375_NL

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    Vyrian FDS6375_NL 50
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    DS637 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    virtex-6 ML605 user guide

    Abstract: UG353 vhdl code 8 bit LFSR ML605 UCF FILE virtex 5 fpga utilization simple 32 bit LFSR using verilog 65Gbps SP006 virtex-5 ML605 user guide aurora GTX
    Contextual Info: LogiCORE IP Aurora 8B/10B v5.3 DS637 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core implements the Aurora 8B/10B protocol using the high-speed serial transceivers on the Virtex -5 LXT, SXT, FXT, and TXT


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    8B/10B DS637 virtex-6 ML605 user guide UG353 vhdl code 8 bit LFSR ML605 UCF FILE virtex 5 fpga utilization simple 32 bit LFSR using verilog 65Gbps SP006 virtex-5 ML605 user guide aurora GTX PDF

    virtex-7

    Abstract: Aurora LX240T virtex7 vhdl coding for error correction and detection xilinx virtex-7 Spartan-6 LXT LX240T-FF1156 kintex 7
    Contextual Info: LogiCORE IP Aurora 8B/10B v8.1 DS797 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core supports the AMBA protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the


    Original
    8B/10B DS797 virtex-7 Aurora LX240T virtex7 vhdl coding for error correction and detection xilinx virtex-7 Spartan-6 LXT LX240T-FF1156 kintex 7 PDF

    XC6SLX45T-3FGG484C

    Abstract: XC6SLX45T-3FGG484 sp605 XAPP492 xilinx mig user interface design SPARTAN-6 GTP XC6SLX45T-3F SFP MCB RAMB16BWERs xilinx DDR3 controller user interface
    Contextual Info: Application Note: Spartan-6 Family Extending the Spartan-6 FPGA Connectivity TRD PCIe-DMA-DDR3-GbE to Support the Aurora 8B/10B Serial Protocol XAPP492 (v1.0) June 23, 2010 Summary Authors: Vasu Devunuri and Sunita Jain Targeted Reference Designs (TRDs) provide Xilinx designers with turn-key platforms to create


    Original
    8B/10B XAPP492 XC6SLX45T-3FGG484C XC6SLX45T-3FGG484 sp605 XAPP492 xilinx mig user interface design SPARTAN-6 GTP XC6SLX45T-3F SFP MCB RAMB16BWERs xilinx DDR3 controller user interface PDF

    Contextual Info: Preliminary Datasheet CPC-44-MR-LR-CLFA Features  Support 40GBASE-LR4 application  Up to 10km transmission on SMF  CWDM DFB laser and PIN receiver  high speed I/O electrical interface  MDIO interface with integrated Digital Diagnostic monitoring


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    CPC-44-MR-LR-CLFA 40GBASE-LR4 DS-6375 PDF

    virtex-6 ML605 user guide

    Abstract: virtex-7 sp605 verilog code 8 bit LFSR UG476 ARM v7 block diagram virtex7
    Contextual Info: LogiCORE IP Aurora 8B/10B v7.1 DS797 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Aurora 8B/10B core supports the AMBA protocol AXI4-Stream user interface. The core implements the Aurora 8B/10B protocol using the


    Original
    8B/10B DS797 virtex-6 ML605 user guide virtex-7 sp605 verilog code 8 bit LFSR UG476 ARM v7 block diagram virtex7 PDF