VIRTEX7 Search Results

Contextual Info: Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 v1.18 November 26, 2013 Product Specification Introduction Virtex -7 T and XT FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance.

Contextual Info: 7 Series FPGAs Clocking Resources User Guide UG472 v1.8 August 7, 2013 The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

XC7K325T-ffg900

Abstract: XC7K325TFFG900 VX690T
Contextual Info: Vivado Design Suite User Guide Release Notes, Installation, and Licensing UG973 v2013.2 June 19, 2013 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

Contextual Info: 7 Series FPGAs Memory Interface Solutions v1.7 DS176 October 16, 2012 Advance Product Specification Introduction LogiCORE IP Facts Table The Xilinx 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 and DDR2

Contextual Info: AN 307: Altera Design Flow for Xilinx Users AN-307-7.0 Application Note Introduction Designing for Altera Field Programmable Gate Array devices FPGAs is very similar, in concept and practice, to designing for Xilinx FPGAs. In most cases, you can simply import your register transfer level (RTL) into Altera’s Quartus® II software

XQ7A200T

Contextual Info: 12 Defense-Grade 7 Series FPGAs Overview DS185 v1.0 May 10, 2013 Advance Product Specification General Description Xilinx Defense-grade 7 series FPGAs comprise three FPGA families that address the complete range of system requirements, ranging from low cost,

verilog code for dual port ram with axi interface

Abstract: XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface XC6VLX75T-2FF784 hamming code in vhdl axi wrapper blk_mem_gen verilog code for pseudo random sequence generator in state diagram of AMBA AXI protocol v 1.0
Contextual Info: LogiCORE IP Block Memory Generator v7.1 DS512 April 24, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Block Memory Generator BMG core is an advanced memory constructor that generates area and performance-optimized memories

UG470

Abstract: local bus to uart using vhdl microblaze XC6VLX240T-1FF UG081
Contextual Info: LogiCORE IP I/O Module v1.00.a DS866 April 24, 2012 Product Specification Introduction LogiCORE Facts The LogiCORE I/O Module is a highly integrated and light-weight implementation of a standard set of peripherals. The I/O Module is a standalone version of the tightly

xc6slx150t

Abstract: STR Y 6763 64 point FFT radix-4 VHDL documentation 16 point FFT radix-4 VHDL documentation verilog code for radix-4 complex fast fourier transform radix-2 DIT FFT vhdl program fft matlab code using 8 point DIT butterfly str 1096 XC6VLX75T vhdl code for simple radix-2
Contextual Info: LogiCORE IP Fast Fourier Transform v8.0 DS808 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Xilinx LogiCORE IP Fast Fourier Transform FFT implements the Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the

XC7V2000T

Abstract: FFG1157 XC7A200T XC7V2000T PCIE FFG1930 kintex 7 Artix-7 XC7V585T FLG1926 XC7A100T
Contextual Info: LogiCORE IP 7 Series FPGAs Integrated Block v1.4 for PCI Express DS821 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express core is a high-bandwidth, scalable, and reliable serial interconnect building block for use

XC7K325TFFG900

Abstract: XC7K325T-ffg900 XC7K325T kintex 7 virtex7
Contextual Info: LogiCORE IP Processor System Reset Module v4.00a DS406 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The Xilinx LogiCORE IP Processor System Reset Module core provides customized resets for an entire processor system, including the processor, the

XC7K410TFFG676-3

Abstract: XILINX ipic axi Xilinx ISE Design Suite 14.2 axi interconnect xilinx xc6vlx130t1ff ZYNQ-7000
Contextual Info: LogiCORE IP AXI Timebase Watchdog Timer axi_timebase_wdt (v1.01.a) DS763 July 25, 2012 Product Specification Introduction LogiCORE IP Facts The Advanced eXtensible Lite (AXI) Timebase Watchdog Timer is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdog timer.

X485T

Abstract: AMBA AXI4 verilog code axi wrapper
Contextual Info: Xilinx Design Tools: Release Notes Guide Vivado Design Suite and ISE Design Suite UG631 v2012.2, v14.2 July 25, 2012 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

ba39 regulator

Abstract: al15 schematic
Contextual Info: VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board User Guide UG957 v1.2 December 18, 2013 DISCLAIMER The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum

10Gbase-kr backplane connector

Abstract: Virtex-7 serdes virtex-7 Auto-Negotiation 10Gbase kr
Contextual Info: LogiCORE IP 10-Gigabit Ethernet PCS/PMA v2.3 DS739 April 24, 2012 Product Specification Introduction The LogiCORE IP 10-Gigabit Ethernet Physical Coding Sublayer/Physical Medium Attachment PCS/PMA core forms a seamless interface between the Xilinx 10-Gigabit Ethernet Media Access

axi ethernet lite software example

Abstract: zynq axi ethernet software example microblaze ethernet V101A microblaze axi ethernet lite microblaze ethernet lite
Contextual Info: LogiCORE IP Ethernet Lite MAC v1.01a DS787 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AMBA AXI Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable features described in the IEEE Std. 802.3

XC4VLX15-FF668

Abstract: axi4 XC4VLX15-FF668-10 FIFO Generator User Guide XQR XQ artix7 ucf file XC6SLX150T-FGG484-2 LocalLink axi wrapper XILINX/fifo generator xilinx spartan
Contextual Info: LogiCORE IP FIFO Generator v8.3 DS317 October 19, 2011 Product Specification Introduction The Xilinx LogiCORE IP FIFO Generator is a fully verified first-in first-out FIFO memory queue for applications requiring in-order storage and retrieval. The core provides an optimized solution for all FIFO

sgmii specification ieee

Abstract: ENG-46158 virtex-7 1000BASE-X sfp sgmii traffic light controller vhdl coding verilog hdl code for traffic light control ISERDES SPARTAN 6 ethernet vhdl ethernet spartan 3a vhdl ethernet spartan 3e
Contextual Info: LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.2 DS264 January 18, 2012 Product Specification Introduction The LogiCORE Ethernet 1000BASE-X PCS/PMA or Serial Gigabit Media Independent Interface SGMII core provides a flexible solution for connection to an Ethernet Media Access

d5200c

Abstract: RAMB16BWER vhdl code SECDED Xilinx ISE Design Suite 14.2 XC6SLX45T RAMB18E1
Contextual Info: LogiCORE IP AXI Block RAM BRAM Controller (v1.03a) DS777 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP AXI Block RAM (BRAM) Controller is a soft IP core for use with the Xilinx Vivado™ Design Suite, Embedded Development Kit

IS61LVPS25636A

Abstract: XPS ipic axi4 example XC6SL* MEMORY state machine axi 3 protocol emc core IDT71V ise 9922 XC7K325T-FFG676
Contextual Info: LogiCORE IP AXI External Memory Controller v1.02a DS762 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The AXI External Memory Controller (EMC) IP core provides a control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular

0x77C

Abstract: iodelay IEEE1722 DS818 KC705 RGMII phy Xilinx UG474 UG777 UG472 verilog code for mdio protocol
Contextual Info: ‘‘‘‘‘‘‘‘Tri-Mode LogiCORE IP Tri-Mode Ethernet MAC v5.3 DS818 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP Tri-Mode Ethernet Media Access Controller TEMAC solution comprises the 10/100/1000 Mb/s Ethernet MAC, 1 Gb/s Ethernet

XC6SLX16-CSG324

Abstract: XC6SLX16CSG324 uart 16550 HOLDING UART16550 16550 uart timing XC7K410TFFG676-3
Contextual Info: LogiCORE IP AXI UART 16550 v1.01a DS748 July 25, 2012 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA (Advance Microcontroller Bus Architecture) AXI (Advanced

verilog code for 10 gb ethernet

Abstract: DS813 3030 xilinx vhdl code for mac transmitter zynq axi ethernet software example 10Gigabit Ethernet PHY ethernet mdio circuit diagram MAC layer sequence number cyclic redundancy check verilog source vhdl code for ethernet mac spartan 3
Contextual Info: LogiCORE IP 10-Gigabit Ethernet MAC v11.2 DS813 October 19, 2011 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP 10-Gigabit Ethernet MAC core is a single-speed, full-duplex 10 Gb/s Ethernet Media Access Controller MAC solution enabling the design

MDIO clause 45 specification

Abstract: xaui marvell "reduced xaui" dune Marvell PHY Xilinx virtex rxaui marvell XGXS Marvell design guide marvell ethernet PHY transceivers Marvell PHY register map DS740
Contextual Info: LogiCORE IP RXAUI v2.3 DS740 April 24, 2012 Product Specification Introduction LogiCORE IP Facts Table The LogiCORE IP RXAUI core is a high-performance, low pin count 10 Gb/s interface intended to allow physical separation between the data-link layer and