PCIO Search Results

74HC7046A

Contextual Info: New Data CD54/74HC7046A CD54/74HCT7046A pciouT Old PC2QUT •2CS-41204 FUNCTIONAL DIAGRAM File Number 1 9 2 0 Phase-Locked Loop with VCO And Lock Detector Type Feature«: • Center frequency of 18 MHz fyp. at Vcc = 5 V • Choice o f two phase comparators:

MAX485 rx tx

Abstract: 74LCX245 DTR con3 MAX3245ECWI C4114 100U 1N914 AT62B pca8
Contextual Info: 5 4 3 2 1 TP1 +5V GND TP2 +5V DRV_RESET X1 ISA_AB_TEST J1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 D C1 C2 C3 C4 100U_16V_ELECT .1U_1206 .1U_1206 .1U_1206 -PCIOW -PCIOR -PCIOW -PCIOR +5V C C5 .1U_1206 C6

STP2003QFP

Abstract: STP2003PQFP MK48T59 100-4183-05 isa bus isa bus data sheet floppy controller pinout pci slot pinout tri state CS4231
Contextual Info: STP2003QFP August 2001 PCIO DATA SHEET PCI I/O Controller DESCRIPTION The PCIO chip is a high integration, high performance single chip IO subsystem connected to the PCI local bus. Using a single PCI bus load it integrates high speed Ethernet and EBus2. EBus2 is a generic slave DMA

Contextual Info: ADVANCE MICRON 32 M EGx64 I SDRAM DIMM MT16LSDT3264A SYNCHRONOUS DRAM MODULE For the latest full-length data sheet, please refer to the Micron Web site: www.micron.com /m ti/m sp/htm l/ datasheet.html FEATURES PIN ASSIGNMENT Front View • PCIOO-compliant; includes CON CURREN T AUTO

26DQ3

Contextual Info: ADVANCE MICRON 32 M EGx72 I SDRAM DIMM MT18LSDT3272A SYNCHRONOUS DRAM MODULE For the latest full-length data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html FEATURES PIN ASSIGNMENT Front View 168-Pin DIMM (H-24) • PCIOO-compliant; includes CONCURRENT AUTO

J1033

Abstract: 74LCX245A J21-12 J631 IOW56 1N914 AT62B TP10 PCA9 LT1086cm
Contextual Info: 5 4 3 2 1 DRV_RESET +5V 1 CON_AT62B J1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 1 TP2 1 TP1 10_16V_ELECT .01_1206 C11 .1_1206 C10 C9 D -PCIOW -PCIOR -PCIOW -PCIOR 1 1 TP5 +5V +5V TP6 .10_1206 C16 .1_1206

CL-GD5434

Abstract: cr3c CR3D POS102 cr37
Contextual Info: CL-GD543X/ '4X rCIRRUS LOGIC Alpine Family VGA GUI Accelerators 6. CL-GD543X/ 4X REGISTERS External/General Registers Abbreviation Register Name POS94 POS102 VSSM VSSM MISC MISC FC FC FEAT STAT 3C6 3C7 3C7 3C8 3C9 PCIOO PCI04 PCI04 PCI08 PCI10 PCI14 PC 130

"LCK"

Contextual Info: PRELIMINARY 16 MEG: x16 SDRAM MICRON I TKtHOLMTT, INC. SYNCHRONOUS DRAM MT48LC1M16A1 S - 51 2K x 16 x 2 banks FEATURES • PCIOO-compliant functionality • Fully synchronous; all signals registered on positive edge of system clock • In tern al p ip elin ed operation; colum n ad d ress can be

micron SDRAM SPD table

Contextual Info: ADVANCE SYNCHRONOUS DRAM MODULE MT9LSDT1672A, MT18LSDT3272A For the latest data sheet please refer to the Micron Web site: www.micronxomfmtifmsp/htmHdatasheethtm! FEATURES PIN ASSIGNM ENT Front V iew 168-Pin DIMM • PC 133- and PCIOO-compliant • JEDEC-standard 168-pin, dual in -lin e m em ory

Arcom Control Systems

Abstract: arcom J557 opto-isolated control EN50081-1 EN50082-1 LK11
Contextual Info: J557 PCIO8 2192-09070-000-000 PCIO8 8-bit ISA bus add-on board with 8 opto-isolated digital inputs and 8 opto-isolated digital outputs Preface Packing List This product is shipped as follows: • Board • User Manual • Utility Disk • PCbus Library Datasheet

Contextual Info: A D VA N CE 16, 32 MEG X 72 SDRAM DIMMs MICRON' I TECHNOLOGY, INC. SYNCHRONOUS DRAM MODULE MT9LSDT1672A, MT18LSDT3272A For the latest data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES • PC133- and PCIOO-compliant

Contextual Info: PRELIMINARY MICRON I 8 , 16 MEG X 64 SDRAM DIMMs TECHNOLOGY, INC. SYNCHRONOUS DRAM MODULE MT8LSDT864A MT16LSDT1664A FEATURES PIN ASSIGNMENT Front View 168-Pin DIMM • PCIOO-compliant, includes concurrent Auto Precharge • JEDEC-standard 168-pin, dual in-line memory module

68C92

Abstract: 147464 TP671 tx2/rx2 1N914 AT62B TP10 74LCX245A U726 tp141
Contextual Info: 5 4 3 2 1 DRV_RESET +5V 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 1 10_16V_ELECT .01_1206 C11 .1_1206 C10 C9 D -PCIOW -PCIOR -PCIOW -PCIOR 1 TP6 1 1 1 TP5 +5V +5V GND 10_16V_ELECT .10_1206 C16 .1_1206 C15

Hitachi DSA0084

Contextual Info: MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVcL PLLCAP PLLVss FWP * VcL VcL Vcc Vcc Vcc Vss Vss Vss Vss AVcc AVcc AVss AVss PB3/IRQ1/POE1 PB2/IRQ0/POE0 PB5/IRQ3/POE3 PB4/IRQ2/POE2 PA1/POE1/TXD2 PA0/POE0/RXD2 PA3/POE4/RXD3 PA2/IRQ0/PCIO/SCK2 PA5/IRQ1/POE6/SCK3 PA4/POE5/TXD3

Contextual Info: ADVANCE 128 MEG: x4, x8, x16 SDRAM MICRON I TECHNOLOGY, INC. SYNCHRONOUS DRAM MT48LC32M4A1 /A2 - 8 Meg x 4 x 4 banks MT48LC16M8A1 /A2 -4 Meg x 8 x 4 banks MT48LC8M16A1/A2 -2 Meg x 16 x 4 banks FEATURES • PCIOO-compliant, includes CONCURRENT AUTO PRECHARGE

STP2003QFP

Abstract: ATM622-S STP2012 ATM 814
Contextual Info: ASICs STP2003QFP: PCIO Peripheral Component Interconnect I/O D

Contextual Info: 64 M E G :X 4e X nnX A M MICRON I TECHNOLOGY, INC. Q ^ ^ jy j MT48LC16M4A1 /A2 -4 Meg x 4 x 4 banks MT48LC8M8A1/A2 - 2 Meg x 8 x 4 banks MT48LC4M16A1/A2 -1 Meg x 16 x 4 banks SYNCHRONOUS DRAM FEATURES • PCIOO-compliant, includes CONCURRENT AUTO PRECHARGE

Contextual Info: PR E LI M IN A R Y 16 MEG X 64 SDRA M DI MMs MICRON I 8, TECHNOLOGY, INC. SYNCHRONOUS DRAM M O D U L E MT8LSDT864A MT16LSDT1664A FEATURES PIN A S S I G N M E N T Front View * PCIO O -com pliant, in clu d es co n cu rren t A u to P rech arg e * JE D E C -stan d ard 168-p in, dual in-line m em o ry m od u le

Contextual Info: ADVANCE MICRON 32 M EGx72 I SDRAM DIMM MT18LSDT3272A SYNCHRONOUS DRAM MODULE For the latest full-length data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet, html FEATURES PIN ASSIGNMENT Front View 168-Pin DIMM (H-24) • PCIOO-compliant; includes CONCURRENT AUTO

LB 124 d

Contextual Info: ADVANCE MICRON 32 M EGx64 I SDRAM DIMM MT16LSDT3264A SYNCHRONOUS DRAM MODULE For the latest full-length data sheet, please refer to the Micron Web site: www.micron.com/mti/msp/html/ datasheet.html FEATURES PIN ASSIGNMENT Front View • PCIOO-compliant; includes CONCURRENT AUTO

MK48T59

Abstract: STP2003QFP FLOPPY pinout 24 82077COMPATIBLE sun sparc pinout
Contextual Info: S un M ic r o ele c t r o n ic s July 1997 PCIO DATA SHEET PCI I/O Controller D e s c r ip t io n The PC IO 111 chip is a high integration, high performance single chip IO subsystem connected to the PCI Local Bus. Using a single PCI bus load it integrates high speed Ethernet and EBus2. EBus2 is a generic slave DMA

MK48T59

Abstract: STP2003QFP sf3a floppy controller pinout pci slot pinout tri state 16C550 CS4231 P1284 PC87303
Contextual Info: 802-7836.frm Page 1 Monday, August 25, 1997 2:50 PM STP2003QFP July 1997 PCIO DATA SHEET PCI I/O Controller DESCRIPTION The PCIO [1] chip is a high integration, high performance single chip IO subsystem connected to the PCI Local Bus. Using a single PCI bus load it integrates high speed Ethernet and EBus2. EBus2 is a generic slave DMA bus Pseudo-ISA

Contextual Info: ADVANCE MICRON1 32 M EGx64 I SDRAM DIMM SYNCHRONOUS DRAM MODULE M T 1 6 L S D T 3 2 6 4 A For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES PIN ASSIGNMENT Front View PCIOO-compliant; includes CONCURRENT AUTO

Contextual Info: PRELIMINARY MICRON I 8, 16 MEG X 72 SDRAM DIMMs TECHNOLOGY, INC. SYNCHRONOUS DRAM MODULE MT9LSDT872A MT18LSDT1672A FEATURES • PCIOO-compliant, includes concurrent Auto Precharge • JEDEC-standard 168-pin, dual in-line memory module DIMM • Nonbuffered