PCI90 Search Results

PQ-32/9060

Contextual Info: PCI9080 l20 bmpatibleFCI BusMast# I/O Activator Chip Features Flexible l20 Connection to the PCI Bus • PC I V ersion 2 1 com p l a n t BusM a s te r interfaae chip fo r ad a p te rs a n d an b ed d e d system s F o r a d d -in c a rd a n d a n b e d d e d sy stan d esig n ers a n d in te g ra to rs alike, th e m is -

MSL260G

Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
Contextual Info: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)

PCI9056

Abstract: PCI9056-BA66BI PCI9056BA66BI r-102 R102 PLX pci9056
Contextual Info: November 12, 2003 Subject: Last Time Buy Reminder PCI9056-AD66BI Dear Valued PLX Customer: This letter is a reminder that PLX intends to cease production of the following part: PCI9056-AD66BI. You can continue to place orders on this device until December 30 2003, and PLX will

93CS46

Abstract: 0x00000018 E 32.0000 C 10B5 c code for pci master
Contextual Info: PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _ Features_ • • • • • • • • PCI9060 bridge between Primary PCI Bus and Intel

0x00000010

Abstract: 0x300000C0 0x0000000b E 32.0000 C 000D 10B5 0x300000C4 0x10000000-0x2FFFFFFF
Contextual Info: PLX Technology PCI9060/68040 DEMO Memory Map 06/24/96 PCI Configuration Registers PCI CFG Offset BIT 0x00000000 0-15 0x00000002 0-15 Function Vendor ID, Allocated to PLX by PCI SIG Read-only (Default = 10B5) Device ID, Allocated by PLX (Read-only) (Default = 9060)

Contextual Info: 0ns TITLE 100ns 200ns 300ns PCI9060 STATIC RAM WRITE 68040 , 4 WORDS, ONE WAIT STATE [SWR4_040.TD] (07/10/95) BCLK-30 [6.5,25] LA[2.31], SIZ0,1 [6.5,25] [6.5,25] TS~ [6.5,25] [6.5,25] [6.5,25] [6.5,25] TIP~ R/W [2,7.5] [2,7.5] SRCS~ [1,5] <14.33,> <12.67,>

16V8H-15

Abstract: 20-2136J res 10k sip 16V8H-15 pc IC 4020 pulse TRANSFORMER valor res 0402 MSL-260-G-H ic 0808 data sheet 16v8h
Contextual Info: PLX Technology PCI9060 DEMO List of Materials 06/16/96 Description Qty Vendor Vendor Part Reference Designator PCB,PCI9060 DEMO,Rev A IC,PCI9060,PQFP IC,80960CA,33 MHz,PQFP IC,82596CA,33 MHz,PFQP IC,82C503,PLCC IC,16550A,PLCC IC,Static Ram, 32Kx8, 15 nsec, 28 Pin 300 Mil SOJ

R101

Contextual Info: 0ns TITLE 50ns 100ns 150ns PCI9060 DRAM REFRESH CYCLE [RFSH.TD] 09/02/95 BCLK-33 [2,11] [2,11] RFSHCLK [1,5] [1,5] RFSHRQ~ CAS_STATE IDLE C9 C10 C11 [1,5] IDLE [1,5] REFRESH~ [1,5] [1,5] CASENL~ [2,7.5] [2,7.5] CASL[0.3]~ [1,5] [1,5] CASENH~ [2,7.5] [2,7.5]

Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns PCI9060/68040 DIRECT SLAVE STATIC RAM READ, 4 WORDS, NO WAIT STATES [DSRD4.TD] 08/01/95 <8.33,> BCLK-30 [8,20] [8,20] [8,20] [8,20] [8,20] LA[2.31], LBE[0.3] [6,16.5] [6,16.5] ADS~ [6,17] [6,17] LW/R [8,20] [8,20] BLAST~

Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns 250ns PCI9060 DIRECT SLAVE INTERLEAVED DRAM 4 WORD WRITE [DSWR4.TD] 08/30/95 BCLK-33 BCLKN-33 [8,20] [8,20] LA[2.31], LBE[0.3] [8,20] [8,20] A0 [8,20] A1 A2 A3 [9,20] [9,20] [9,20] LD[0.31] NEW ADDRESS [9,20] D0 D1 [9,20]

diode S2

Contextual Info: 0ns TITLE 100ns 200ns 300ns PCI9060 DIRECT SLAVE STATIC RAM WRITE, 4 WORDS, ONE WAIT STATE [DSWR4.TD] 08/01/95 BCLK-30 [8,20] LA[2.31], LBE[0.3] [6,16.5] [6,16.5] ADS~ [6,17] [6,17] LW/R [8,20] [8,20] BLAST~ [2,7.5] [2,7.5] SRCS~ [1,5] <14.33,> <12.67,>

D0807

Abstract: C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705
Contextual Info: PLX Technology PCI9060 Demo Board REV 1 1 2 3 4 5 6 7 8 9 10 11 Schematics 06/16/96 Title Page PCI9060, EEPROM 80960CA CPU Local Bus Control SRAM FLASH EPROM, UART 82596CA Ethernet Controller Ethernet Physical Layer PCI Bus Connector Reset, Test Headers Capacitors, Resistors

doorbell application

Contextual Info: SECTION 3 FUNCTIONAL DESCRIPTION 3. SECTION 3 - FUNCTIONAL DESCRIPTION 3.1 PCI 9060 Initialization The PCI9060 configuration registers can be programmed by an optional serial EEPROM and/or by a local processor. EEPROM Initialization During serial EEPROM initialization, the PCI9060 response to PCI target accesses is RETRYs. During serial EEPROM

Contextual Info: BUS OPERATION SECTION 2 2. SECTION 2 - BUS OPERATION 2.1 PCI BUS CYCLES The PCI9060 is PCI Compliant. 2.1.1 PCI Target Command Codes As a target, the PCI9060 allows access to the PCI9060 internal registers and the local bus using the following commands;

PCI9080-3

Abstract: 8 bit data bus using vhdl pci9080 C6000 TMS320C6000 TMS320C6202 TMS320C6203C programming tms320c6000
Contextual Info: Application Report SPRA539A - August 2001 TMS320C6000 Expansion Bus Interface to PCI Bus Through PLX PCI9080 Bridge Chip Zoran Nikolic Digital Signal Processing Solutions ABSTRACT This application report describes how to interface the Texas Instruments TI

Contextual Info: 0ns TITLE 100ns 200ns 300ns 400ns POWERPC , 1 WORD DRAM READ BY PCI9060 [PCIRD1.TD] 01/23/96 STATE LCLK-25 [5,17] [5,17] LHOLD [8,20] [8,20] [8,20] [8,20] LA[31:2] LBE[3:0] [6,17] [6,17] LW/R [6,13] [6,13] ADS~ [8,16] [8,16] BLAST~ [2,6.5] DRAMCTL STATE

68040* part numbering

Abstract: 93CS46 SR96 L16 eeprom Motorola 68040 Pal programming 10B5
Contextual Info: Go to next Section: Designing a PCI Memory Board Return to Table of Contents Using the Motorola 68040 with the PCI 9060 Schematics etc. PCI9060/68040 AN July 1995 PCI9060/68040 Application Note VERSION 1.0 _ _ _

DATA18

Contextual Info: 0ns TITLE 250ns 500ns 750n POWERPC , 3 WORD WRITE TO DRAM FROM PCI9060 [PCIWR3.TD] 01/23/96 STATE LCLK-25 [5,17] [5,17] LHOLD [9,20] [9,20] LD[31:0] WRITE DATA 1 [8,20] [8,20] LA[31:2] [9,20] [9,20] DATA2 ADDR1 DATA3 [8,20] [8,20] ADDR2 ADDR3 [8,20] [8,20]

DT 94

Abstract: 80960CA
Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns PCI9060 FLASH EPROM WRITE 80960CA , 1 WORD [PWR_960.TD] (07/12/94) STATE A 3 2 1 D A PCLK1-33 [3,14] [3,14] LA[2.31], LBE[0.3] [3,16] [3,16] LD[0.7] [6,18] [6,18] [6,18] [6,18] [3,18] [3,18] ADS~ LW/R [5,16] [5,16] BLAST~

S337

Abstract: Diode S4 DT 94 80960CA
Contextual Info: 0ns TITLE 100ns 200ns 300ns 400ns PCI9060 UART READ 80960CA , 1 WORD [URD_960.TD] (07/12/94) STATE 6 7 A 5 4 3 2 1 D A <2.92,> <-0.5,> PCLK1-33 [3,14] [3,14] LA[2.31], LBE[0.3] [6,18] [6,18] ADS~ [3,18] [3,18] LW/R [5,16] [5,16] BLAST~ [3,14] [3,14] DT/R

LD31

Contextual Info: 0ns TITLE 50ns 100ns 150ns 200ns 250ns 300ns POWERPC , 1 WORD READ FROM PCI9060 INTERNAL REGISTERS [PPCRD1.TD] 01/24/96 STATE LCLK-25 [4,15] [4,15] A[6:29] [3,11] [3,11] [3,12] [3,12] [2,12] [2,12] PR/W WBE[0:3] CS1~ [3,10] [3,10 CS9060~ [0,0] [0,0] LA[25:2]

16v8

Abstract: 20V8 U0401 286E application PAL 16v8 Transistor Equivalent list u0507 U0404 U1002 U0405
Contextual Info: PLX Technology PCI9060 DEMO 1 2 3 4 5 6 7 PAL List 06/16/96 NAME TYPE REV arb ioctl msel ready reset srctl srwe 20V8-10 20V8-10 20V8-7 16V8-7 16V8-15 16V8-7 16V8-7 1 1 CHKSUM 822A 9d8c 60b8 42dc 20db 4469 286e SHEET REFERENCE 4 4 4 4 10 5 5 U0405 U0402 U0401

Contextual Info: 0ns TITLE 100ns 200ns 300ns 400ns 500ns POWERPC , 1 WORD WRITE TO DRAM FROM PCI9060 [PCIWR1.TD] 01/23/96 STATE LCLK-25 [5,17] [5,17] LHOLD [9,20] [9,20] LD[31:0] WRITE DATA [8,20] [8,20] [8,20] [8,20] LA[31:2] LBE[3:0] [6,17] [6,17] LW/R [6,13] [6,13] ADS~

Y0803

Abstract: R0801 U0801A Y0802 PU0806 C0801 STI3400 R0806 U0802 R0803
Contextual Info: 1 2 1 7 Y0801 NC VCC GND OUT 3 14 4 5 6 7 8 VCC 8 1 CLK50R 50 MHz R0801 2 CLK50 FOR STI3400 33 A 4 A CLK25R~ 1 PU0801 4 3 D PR 2 CLK25A FOR PCI9060, FIFO 33 U0801A Q R0802 2 5 CLK25R 1 R0803 2 CLK25B FOR MACHS 33 CLK CL Q 2,4,9 3 6 74ACT74 1 PU0802 1 7 B VCC