ODULO16 Search Results

54AC161

Abstract: 54ACT161 AC161 ACT161
Contextual Info: & Semiconductor 54AC161 • 54ACT161 Synchronous Presettable Binary Counter General Description S ynchronous counting and loading High-speed synchronous expansion The ’A C /’ACT161 are high-speed synchronous m odulo-16 binary counters. They are synchronously presettable fo r a p ­

74160PC

Abstract: 74LS160 parallel counter 74LS160PC BCD Decade logic diagram 74160 74LS160D 74LS162 74LS160DC 74160 74LS162 parallel counter logic diagram of 74ls160
Contextual Info: 160 162 • CO NN ECTIO N DIAGRAM / n i * 54/74160 54LS/74LS160 S4LS/74LS162 ^ ^ 4 /7 4 1 6 2 P IN O U T A \ / ô / o ô ï o / ^S Y N C H R O N O U S PRESETTABLE BCD DECADE COUNTERS DESC R IP TIO N — The ’160 and '162 are high speed synchronous decade

Contextual Info: H D 74A C 168/H D 74A C 169 D escription T he H D 74A C168 and H D 74A C169 are fully syn­ chronous 4-stage u p /d o w n counters. The H D 74A C168 is a BCD decade c o u n te r, the H D 74A C169 is a m odulo-16 binary counter. B oth feature a preset capability for program m able opera­

Contextual Info: ENHANCED 4-STAGE COUNTER/SHIFT REGISTER SYNERG Y SY100S336A SEMICONDUCTOR FEATURES DESCRIPTION Max. shift frequency of 700MHz Clock to Q delay max. of 1100ps Sn to TC speed improved by 50% Sn set-up and hold time reduced by more than 50% Iee min. of -170m A

Contextual Info: r T , 1Q Q Q Revised Ju ly 1999 EMICONDUCTGRTM 74F169 4-Stage Synchronous Bidirectional Counter General Description Features T h e 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a m odulo-16 binary counter. Fea­ tures a preset capability for program m able operation, carry

74LS160D

Abstract: 74LS160PC IC 74LS160 74160PC 74LS160 parallel counter 74LS160P Ls 74160 74LS162D 74162FC logic diagram of 74ls160
Contextual Info: 160 • 162 CONNECTION DIAGRAM \ftoic oïb PINOUT A 54/74160 • 54LS/74LS160 ¿ ,6 ^ /7 4 1 6 2 • 94LS/74LS162 0/co4- / ^SYNCHRONOUS PRESETTABLE BCD DECADE COUNTERS H E îfilv c c C P |7 î ï DESCRIPTION — The ’160 and '162 are high speed synchronous decade

74LS193D

Contextual Info: 193 CONNECTION DIAGRAM PINOUT A J /5 4 /7 4 1 9 3 - / 5 4 L S / 7 4 L S 1 9 3 6 / 6 <7 q4 UP/DOWN BINARY COUNTER (With Separate Up/down Clocks 16] Vcc H] Po Qo[7 Î 4 l MR cpd |T 751 TCp cpu [T j DESCRIPTION — The ’193 is an up/dow n m odulo-16 binary counter. Sep­

LS161

Contextual Info: LS161 Binary Direct Clear Synchronous 4-Bit Counter T he LS161 is a bipolar, NPN, sealed-junction, silicon integrated circu it. It is m anufactured in low-power S chottky te ch no lo g y and is available in a wirebonded, 16-pin p lastic DIP or surface m ount

74F191

Abstract: 74F191SC 74F191SJ M16A M16D MS-001 N16E
Contextual Info: r T , 1 Q Q Q Revised July 1999 EMICONDUCTGRTM 74F191 Up/Down Binary Counter with Preset and Ripple Clock General Description Features T he 74F191 is a reversible m odulo-16 binary counter fe a ­ turing synchronous counting and asynchronous presetting. T he preset feature allow s the 74F191 to be used in pro­

74F569

Abstract: 74F569PC 74F569SC 74F569SJ M20D Z6 DIODE
Contextual Info: S E M IC O N D U C T O R tm 74F569 4-Bit Bidirectional Counter with 3-STATE Outputs General Description The ’F569 is a fully synchronous, reversible counter with 3-STATE outputs. The ’F569 is a binary counter, featuring preset capability fo r program m able_operation, carry looka­

diode t25 4 L0

Abstract: 74AC163 74AC163MTC 74AC163SC 74AC163SJ 74ACT163 ACT163 M16A M16D MTC16
Contextual Info: A I R C H I L D Revised N ovem ber 1999 S E M I C O N D U C T O R TM 74AC163 • 74ACT163 Synchronous Presettable Binary Counter General Description Features The A C /AC T163 are high-speed synchronous m odulo-16 binary counters. T hey are synchronously presettable for

74F169

Abstract: 74F169PC 74F169SC 74F169SJ M16A M16D MS-001 N16E
Contextual Info: r T , 1 Q Q Q Revised July 1999 EMICONDUCTGRTM 74F169 4-Stage Synchronous Bidirectional Counter General Description Features T h e 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a m odulo-16 binary counter. Fea­ tures a preset capability fo r program m able operation, carry

mr 504 diode

Abstract: LS390
Contextual Info: M MOTOROLA D E S C R IP T IO N — The S N 5 4 L S /7 4 L S 3 9 0 and S N 54LS /74LS 393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-tw o section and a divide-byfive section, w ith a separate clock input for each section. The tw o

Contextual Info: CY54/74FCT163T 4-Bit Binary Counter CYPRESS Features • Function, pinout, and drive compatible with FCT and F logic • FCT-C speed at 5.8 ns max. Com’I FCT-A speed at 7.2 ns max. (Com’I) • Reduced Vqh (typically = 33V) versions of equivalent FCT functions

Contextual Info: M M ilitary 54F163A M O TO R O LA Synchronous 4-Bit Binary Counter (Synchronous M aster Reset) MPO mini ELECTRICALLY TESTED PER: MIL-M-38510/34302 The 54F163A is a high-speed synchronous m odulo-16 binary counter. It is synchronously presettable for application in programmable dividers and

HD74ACT161

Contextual Info: HD74ACT161 H D 74A C 163/H D74ACT163 Description Pin Assignment The HD74ACT161 and HD74AC163/HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count

74193PC

Abstract: 74ls193p 74LS193PC ic 74193
Contextual Info: I ' NATI ONAL S E HI C OND {LOGIC} D5E D | bSG112E DOLLES E | 7 ^ ^ 5 -2 3 -0 7 193 CO NN ECTIO N DIAGRAM PINO UT A 54/74193 54LS/74LS193 1 Ü ] Vcc UP/DOWN BINARY COUNTER With Separate Up/down Clocks D E S C R IP T IO N — The '193 is an up/dow n m odulo-16 binary counter. Sep­

Contextual Info: tß Semiconductor 54AC169 • 54ACT169 4-Stage Synchronous Bidirectional Counter General Description S ynchronous counting and loading The ’A C /’A C T169 is fully synchronous 4-stage up/dow n counter. T h e ’A C /’A C T169 is a m odulo-16 binary counter. It

Contextual Info: - ì NATIONAL SEflICOND { L O G I C * OSE D | ¿,501125 0 0 ^ 3 7 T | _ - T - V 5 - ^ 3 -l3 _ 1 9 7 CO NNECTIO N DIAGRAM PINOUT A 54/74197 54LS/74LS197 [7 ch T 7T| V cc PL PRESETTABLE BINARY COUNTERS 13] MR P2 | T DESCRIPTION — The '197 rippie counter contains divide-by-tw o and divideby-e igh t sections w h ich can be com bined to form a m odulo-16 binary

F100K

Abstract: J24E W24B
Contextual Info: Semiconductor 100336 Low Power 4-Stage Counter/Shift Register General Description The 100336 operates as either a m odulo-16 up/down counter o r as a 4 -bit bidirectional shift register. Three Select Sn inputs determ ine the mode of operation, as sh ow n in the

ls293

Abstract: ls290 binary to BCD 8421 LS293-4-BIT LS90 LS93 3 bit ripple counter T74LS293
Contextual Info: ses LS290-DECADE COUNTER LS293-4-BIT BINARY COUNTER DESCRIPTION T 5 4 L S /T 7 4 L S 2 9 0 and T 5 4 L S /T 7 4 L S 2 9 3 are - gn-speed 4-bit ripple type counters partitioned in•: rwo sections. E ach counter has a divide-by-two section and either a divide-by-five L S 2 90 or

programmable binary counter 74193

Abstract: 74193PC 74193 state diagram 74LS193 pin data 74LS193PC 74193 74ls193p 74193 state diagram up counter 74LS193 74LS193B
Contextual Info: 193 CONNECTIO N DIAGRAM PINOUT A 54/74193 à 9X 5 4 L S /7 4 L S 1 9 3 ô /ô -E Oi UP/DOW N BINARY COUNTER H ] V cc njpo [T Ï71 MR O o (T (With Separate Up/down Clocks T 5 ]tc d CPd E [I [F Til PL 03 [7 33p 2 CPU DESCRIPTION — The ’193 is an up/dow n m odulo-16 binary counter. Sep­

tablet counter circuit diagram

Abstract: internal circuitry for sr flip flop CY74FCT163CTPC CY74FCT163CTQC
Contextual Info: CY54/74FCT163T S F A C Y PR E SS Features • Function, pinout, and drive compatible with FCT and F logic • FCT-C speed at 5.8 ns max. Com*l FCT-A speed at 7.2 ns max. (Com’l) • Reduced V oh (typically = 3.3V) versions o f equivalent FCT functions

74LS393PC

Abstract: MODULO-16 54LS393DM 74LS39 74LS393 54LS393FM 74LS393DC 74LS393FC 74LS393P 16 counter
Contextual Info: 393 C O N N E C T IO N D IA G R A M P IN O U T A 54LS/74LS393 0 DUAL M ODULO-16 COUNTER cp [7 101 V c c MR | T 13] CP Qo T Til MR Qi [7 TT|Qo os [T 31] Qi Û3 | T T] Û2 GND ( T D E S C R IP T IO N — The '393 c o n ta in s a p a ir o f h ig h speed 4 -sta g e rip p le