74LS39 Search Results

4LS395

Contextual Info: SN54LS395A, 74LS395A 4-BIT CASCADABLE SHIFT REGISTERS WITH 3-STATE OUTPUTS OCTOBER 1976 - REVISED MARCH 1960 Three-State, 4 Bit. Cascadable, Parallel-ln, Parallel-Out Registers S N 5 4LS 3 95 A . . . J OR W PA CK A G E SN 74LS39SA . . . D OR N PA CKAGE T O P V IE W !

74LS395A

Contextual Info: Signetics 74LS395A Shift Register 4-Bit Cascadable Shift Register With 3-State Outputs Product Specification Logic Products FEATURES TYPE • 4-blt parallel load shift register • Independent 3-state buffer outputs • Separate Q3 output for serial expansion

Contextual Info: 60SHSZUUV Am 25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS • • • 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including:

DN74LS395A

Abstract: MA161
Contextual Info: 74LS395A LS TTL DN74LS Series 74LS395A 4 -b it Cascadable Shift R egisters with 3 -sta te Outputs • D escription P -2 D N 74LS395A is a 4-bit serial/parallel input to serial/parallel o u tp u t shift register w ith 3-state outputs. ■ Features •

74LS399

Contextual Info: Arrt25LS09 Am25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS • • • 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including:

74LSOO

Abstract: HD74LS390 Hitachi Scans-001
Contextual Info: • Dual Decade Counters I BLOCK DIAGRAM {'A This circuit contains eight master-slave flip-flops and ad­ ditional gating to implement two individual four-bit counters. The H D 74LS390 incorporates dual divide-by-two and divideby-five counters, which can be used to implement cycle

74LS390

Abstract: 74LS393 equivalent 74LS393 LS290 LS293 LS390 LS393
Contextual Info: SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54 / 74LS390 and SN54 / 74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input

Contextual Info: SN54LS395A, 74LS395A 4-BIT CASCADABLE SHIFT REGISTERS WITH 3 STATE OUTPUTS OCTO BER 1976 - RE V ISE D M A R C H 1988 Three-State, 4 Bit, Cascadable, ParalleMn, Parallel-Out Registers SN 54LS395A . . . J OR W PACKAGE SN 74LS395A . . . D OR N PACKAGE T O P V IE W

ttl 74LS173

Abstract: ttl 7497 74ls390 D187 D188 D190 D194 D195 D196
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D187 9397, 7497 D188 93167, 74167 0189 54LS/74LS173 9 10 14 15 k h 12 1 1 — 0 CE TC CP ;=3ID OE Gy D194 54LS/74LS390 each half) 15 1 ,1 5 - CPo 4 ,1 2 - CPi M R Oo Q i Qz 03 2 ,1 4 5,11 3, 13 V c c = Pin 16

1N3064

Abstract: 1N916 74LS 74LS395A N74LS395AN
Contextual Info: 74LS395A S ignetics Shift Register 4-Bit Cascadable Shift Register With 3-State Outputs Product Specification Logic Products FEATURES • 4-bit parallel load shift register • Independent 3-state buffer outputs • Separate Q3 output for serial expansion

74ls393 counter pin configuration

Abstract: TE 555-2 TTL 74LS 00 1N3064 1N916 74LS 74LS393 N74LS393D N74LS393N logic diagram of 4bit binary ripple up counter
Contextual Info: Signetics 74LS393 Counter Dual 4-Bit Binary Ripple Counter Product Specification Logic Products FEATURES • Two 4-bit binary counters • Divide-by any binary module up to 28 in one package • Two Master Resets to clear each 4-bit counter individually TY PE

74Ls399

Abstract: 74LS398
Contextual Info: M M O T O R O L A SN54/74LS398 SN54/74LS399 QUAD 2-PORT REGISTER The SN54/74LS398 and SN54/74LS399 are Quad 2-Port Registers, They are the logical equivalent of aquad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit in­

74LS399

Abstract: 5311s 74LS398
Contextual Info: M MOTOROLA SN54LS/74LS398 SN54LS/74LS399 D E S C R IP T IO N — T h e S N 5 4 L S /7 4 L S 3 9 8 and S N 54 L S /7 4 L S 39 9 are Quad 2-Port Registers They are the logical equivalent of a quad 2-input m ultiplexer follow ed by a quad 4-bit edge-triggered register. A Common

TE 555-4

Contextual Info: Signetics 74LS395A Shift Register 4-Bit Cascadable Shift Register With 3-State Outputs Product Specification Logic Products FEATURES TYPE • 4-bit parallel load shift register • Independent 3-state buffer outputs • Separate Q j output for serial expansion

Contextual Info: GD54/74LS390 DUAL 4-BIT DECADE AND BINARY COUNTERS Features Pin Configuration • Dual Versions of the Popular ‘LS90 • ‘LS390. Individual Clocks for A and B Flip-Flops Provide Dual-r 2-^5andCounters • Direct Clear for Each 4-Bit Counter • Dual 4-Bit Version Can Significantly Improve

25LS09

Contextual Info: Am25LS09 Quad Two-Input, High-Speed Register DISTINCTIVE CHARACTERISTICS 4-bit register accepts data from one-of-two 4-bit input fields Edge triggered clock action Second sourced by T.l. as 54LS/74LS399 Am25LS D.C. parameters including: - Vol “ 0.45V at Iol “ 8mA

Contextual Info: 74LS390 Signetics Counter Dual Decade Ripple Counter Product Specification Logic Products FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two Master Resets to clear each decade counter individually

74LS399

Contextual Info: 54LS/74LS399 LOGIC SYMBOL Preliminary data DESCRIPTION FEATURES The “ 399” is a Quad 2-Port Register which combines the functions of a quad 2-input multiplexer and a 4-bit positive edge trig ­ gered register. The state of the common Se­ lect input (S) determines the source of the

74LS395DC

Abstract: 54LS395DM 54LS395FM 74LS395FC 74LS395PC
Contextual Info: 395 C\ 'S 54LS/74LS395 C O N N E C T IO N D IA G R A M P IN O U T A J MR 4-B IT SH IFT REGISTER With 3-State Outputs (T Til v c c Til oo Ds | T G[ P i [7 Î7 ) Oi P î[T 7 | ] 03 P 3 [6 33 ° 3 Po D E S C R IP T IO N — T he ’395 is a 4 -b it re g iste r w ith 3-state o u tp u ts and can

74LS393PC

Abstract: MODULO-16 54LS393DM 74LS39 74LS393 54LS393FM 74LS393DC 74LS393FC 74LS393P 16 counter
Contextual Info: 393 C O N N E C T IO N D IA G R A M P IN O U T A 54LS/74LS393 0 DUAL M ODULO-16 COUNTER cp [7 101 V c c MR | T 13] CP Qo T Til MR Qi [7 TT|Qo os [T 31] Qi Û3 | T T] Û2 GND ( T D E S C R IP T IO N — The '393 c o n ta in s a p a ir o f h ig h speed 4 -sta g e rip p le

74LS574

Abstract: ttl 74LS173 74ls399 93L38 ttl 74165 ttl 7491 54LS 74LS266 ttl 74173 74LS568
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL D93 54LS/74LS379 D94 9386, 74LS266, 54LS/74LS386 D95 54LS/74LS398 Vcc 1 4 5 12 13 4 5 7 6 14 15 17 16 lOa Ila lob lib lo c lie lod lid r ei fi r E5i r?i n S CP Qa Qb 2 GND Vcc = Pin 20 GND = Pin 10 Vcc = Pin 16

Contextual Info: 393 CO NNECTIO N DIAGRAM PINO UT A 54LS/74LS393 0 DUAL MODULO-16 COUNTER D E SC R IPTIO N — The '393 contains a pair of high speed 4-stage ripple counters. Each half of the '393 operates as a m odulo-16 binary divider, with the last three stages triggered in a ripple fashion. The flip -flo ps are

N74LS390N

Abstract: 1N3064 1N916 74LS 74LS390 N74LS390D decade counter circuit diagram CP012
Contextual Info: Signetics 74LS390 Counter Dual Decade R ipple C ounter Product Specification L o g ic P roducts FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 o r 100 • Two Master Resets to clear each

74LS390

Abstract: binary to BCD 8421 74LS393 equivalent SN54-74LS390 74LS393 LS390 LS290 LS293 LS393
Contextual Info: SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER The SN54 / 74LS390 and SN54 / 74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input