NCS287 Search Results

intel 80386 pin diagram

Abstract: 80386-sx buffer intel 80286 pin diagram intel 80286 block diagram XA11 intel 80286 control data bus SL9025 Logicstar
Contextual Info: ADDRESS CO NTRO LLER _ S L 9 0 2 5 PRELIMINARY FEATURES • Supports 80386,80386 SX P9 , and 80286-based AT designs. • Address In to Address Out time is 15 ns. • 24 mA buffers. • Include SA & XA buffers. • Provides Refresh for 256K, 1M or 4Mbit DRAM chips.

VIA SL9011

Contextual Info: The FlexSet PC/AT System Controller SL9011 PRELIMINARY FEATURES • AT System Control Logic. • Supports 80286,80386SX P9 , or 80386DX-based Designs. • Up to 25 MHz Performance. • Clock Switching and Reset Logic. • Programmable Wait States for 8 Bit AT Cycles.

T44A

Abstract: 80286 microprocessor pin out diagram sl9030 t53a 80387SX weitek ti6a 80387DX 80386 microprocessor pin out diagram via flexset
Contextual Info: The FlexSet PC/AT System Controller SL9011 PRELIMINARY FEATURES • AT System Control Logic. • Supports 80286, 80386SX P9 , or 80386DX-based Designs. • Up to 25 MHz Performance. • Clock Switching and Reset Logic. • Programmable Wait States for 8 Bit AT Cycles.

intel 8284 clock generator circuit diagram

Abstract: intel 8284 clock generator intel 8284 clock generator block diagram intel 8284 A clock generator intel 80286 pin diagram 8284 clock generator 8284 intel clock generator intel 80286 block diagram PIN DIAGRAM OF 80286 FE3020
Contextual Info: i« rAl\Al AY IIIIIIIIIIIIIIITHA 1 T | A T ~ \ A 'X T FE3000A AT CPU CONTROL LOGIC 100% h a rd w are and s oftw are c o m p a tib le to th e IB M PC -A T W ait State G e n e ra to r-In te rn a l or External 8 2 8 4 and 8 2 2 8 4 -c o m p a tib le C lo c k G e n e ra to r

VIA SL9030

Abstract: 80386SX core logic SL9025 313233 sl90 SL9030 PG52
Contextual Info: y/ a SL9025 Address Controller PRELIMINARY FEATURES • Supports 80286,80386SX P9 , 80386DX, and 80486-based AT Designs. • Address In to Address Out: 15 ns. • Up to 25 MHz Performance. • 24 mA Buffers. • Include SA & XA Buffers. • Includes XD to XA Transfer Latches.

Contextual Info: SYSTEM CONTROLLER SL9010 GICSTAR PRELIMINARY FEATURES • AT system control logic. • Supports 80386,80386 SX P9 , or 80286-based designs. • 1 6,20,25 MHz options. • Clock switching and reset logic. • Programmable wait states for Memory and I/O. • Programmable command delays for Memory.

386SX

Abstract: 80386-sx buffer SL9010 OPT387 SL901
Contextual Info: SYSTEM CONTROLLER LQGICSTAR _ SL 901° PRELIMINARY FEATURES • AT system control logic. • Supports 80386,80386 SX P9 , or 80286-based designs. • 16,20,25 MHz options. • Clock switching and reset logic. • Programmable wait states for Memory and I/O.

intel 8284 clock generator

Abstract: intel 8284 clock generator circuit diagram intel 80286 pin diagram intel 8284 clock generator block diagram FE3020 intel 8284 A clock generator FE3000A intel 80286 pin function 82284 FE3010
Contextual Info: FAR AD AY 111 53$ °r '" J0È3OOOA AT CPU CONTROL LOGIC 100% h ard w are and so ftw are c o m p a tib le to th e IB M PC -A T W ait State G e n e ra to r-In te rn a l or External 8 2 8 4 and 8 2 2 8 4 -c o m p a tib le C lo ck G e n e ra to r 2 5 6 K and 1 M B R A M su p p o rt

weitek

Abstract: 80387DX sl9350 t46a 80X87 INTEL HT39A refresh logic sl90 t53a SL9030
Contextual Info: y/ à SL9011 System Controller PRELIMINARY FEATURES • AT System Control Logic. • Supports 80286,80386SX P9 , or 80386DX-based Designs. • Up to 25 MHz Performance. • Clock Switching and Reset Logic. • Programmable Wait States for 8 Bit AT Cycles.

SL9025

Contextual Info: ADDRESS CONTROLLER LOGICSTAR _SL9025 PRELIMINARY FEATURES • Supports 80386,80386 SX P9 , and 80286-based AT designs. • Address In to Address Out time is 15 ns. • 24 mA buffers. • Include SA & XA buffers. • Provides Refresh for 256K, 1M or 4Mbit DRAM chips.