LOGICSTAR Search Results

SL9025

Contextual Info: ADDRESS CONTROLLER LOGICSTAR _SL9025 PRELIMINARY FEATURES • Supports 80386,80386 SX P9 , and 80286-based AT designs. • Address In to Address Out time is 15 ns. • 24 mA buffers. • Include SA & XA buffers. • Provides Refresh for 256K, 1M or 4Mbit DRAM chips.

nrzi to nrz circuit diagram

Abstract: SL2002 Logicstar
Contextual Info: SL2002*. DUAL CHANNEL NRZI ENCODER / DECODER J Ü É 3L1M IN A R Y FEATURES PIN CONFIGURATION • Two in d e p e n d e n t D ig ita l Phase Lock Loop c irc u its ■ Two in d ep e nd e nt Full D uplex channels ■ NRZI E n c o d e r/D e co d e r ■ D PLL runs o ff 16x clo ck

Contextual Info: STARLAN INTERFACE SL4000 PRELIMINARY PIN OUT FEATURES o INTERFACE FOR THE LAN CONTROLLERS XTAL1 8X CLKIN _ 1 XTAL2- 2 19 - PSEL RXDOUT- 3 18 - RXDtN TX D IN - 4 17 - TXDOUT 20 - VDD RTS - 5 o UP TO 4 MBITS PER SECOND DATA RATE

CHIPset for 80286

Abstract: SL6003 A1719 logicstar TL4A sl6005
Contextual Info: ADDRESS & DATA BUS BUFFERS SL6003, SL6004, SL6005 17 PC/A T COMPATIBLE CHIP-SET W PRELIMINARY The SL6003 provides address latches and control buffers for the PC / AT system. Control signals from the SL6001 are buffered by the SL6003 and tri-stated for the expansion and the I/O buses. This

74ls612

Abstract: Memory Mapper 348D
Contextual Info: MEMORY MAPPER FOR PC-AT ' SL6012 O t-A C PRELIM INARY 005146 C p\ ^U FEA T U R ES PIN O U T ^ Expands 4 Address Lines to 8 Address Lines RS 2 VDD 2 M A3 MA 2 R S3 R SI CSN M AI 3 4 Designed for PC / AT Paged Memory Mapping 3-State Map Outputs High Speed Low Power CMOS

i8042

Abstract: CHIPset for 80286 80286 address decoder interfacing of memory devices with 80286 CS287 SL6001 SL6002 80287 logicstar
Contextual Info: SYSTEM CONTROL & MEM ORY DECODE SL6001, SL6002 B _ P C /A T COMPATIBLE CHIP-SET PRELIMINARY The SL6001 is used to control the PC / AT system's control system timing, coprocessor interface and NMI detection while the SL6002 decodes RAM /ROM accesses, parity checking and I/O decode logic.

SA17

Contextual Info: GICSTAR PAGE M O D E MEMORY CONTROLLER SL9350 PRELIMINARY FEATURES • 16,2 0 ,2 5 M H z O ptions. • E nhanced fast page m od e design. • Program m able w ait state options. • S h ad ow Ram feature. • Supports 16 M b yte o f on board m em ory. • Can u se 256K x 1, 1 M eg x 1,and 256K x 4 D R A M s or a m ix.

80286 data bus MD

Abstract: MD10 MD11 MD14 SD14 SD15 SS2222
Contextual Info: D A T A CONTROLLER _ S L 90 20 PRELIMINARY FEATURES • Supports 80386,80386 SX P9 , or 80286-based AT designs. • Data In to Data Out time is 15 ns. • 24 mA output buffers. • Includes MD, SD & XD buffers. • 16 bit data path can be vised as Low or H igh buffer.

intel 80386 pin diagram

Abstract: 80386-sx buffer intel 80286 pin diagram intel 80286 block diagram XA11 intel 80286 control data bus SL9025 Logicstar
Contextual Info: ADDRESS CO NTRO LLER _ S L 9 0 2 5 PRELIMINARY FEATURES • Supports 80386,80386 SX P9 , and 80286-based AT designs. • Address In to Address Out time is 15 ns. • 24 mA buffers. • Include SA & XA buffers. • Provides Refresh for 256K, 1M or 4Mbit DRAM chips.

Contextual Info: DATA CONTROLLER _ SL9020 PRELIMINARY FEATURES • Supports 80386,80386 SX P9 , or 80286-based AT designs. • Data In to Data Out time is 15 ns. • 24 mA output buffers. • Includes MD, SD & XD buffers. • 16 bit data path can be used as Low or High buffer.

MV64460

Abstract: Marvell MV64460 Marvell 64460 nec c277 IBM25PPC750G PPC750GX ppc750fx u39 c531 EPSON C172 MAIN Board Circuit Diagram samsung R519
Contextual Info: ® PPC750GX and PPC750FX Evaluation Board User’s Manual SA14-2744-03 Preliminary March 26, 2004 Title Page ® Copyright International Business Machines Corporation 2002, 2004 All Rights Reserved Printed in the United States of America March 2004 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or

paradise ppc1

Abstract: SI5001 SL5001 PRINTER CONTROLLER PARADISE 3ATA dat07 ppc1 ppc1 paradise
Contextual Info: P arallel P rin te r P o rt In terface _ c7 9 s ^> É8ÉIÈ50O1 V 005147 FEATURES P, ^ PIN OUT L _ J » TM Full IBM PC Parallel Port Compatible • Pin-to-Pin Compatible with Paradise System's PPC1. • High Speed low power CMOS technology 24 mA Sink & -12 mA Source current for

6845 crt controller

Abstract: 6845 hercules logicstar 6845 CRT controller
Contextual Info: M ONOGRAPHICS CONTROLLER - * *S L 7001 oc 005148 FEATURES A> fi • Bit-Map Graphics 100% Compatible with HERCULES Monochrome High Resolution: 720 X 350 • Ideal For Low Cost Graphics and Schematic Entry 100% Compatible with IBM MONO-TEXT Adaptor • Implemented in High Speed,

Contextual Info: SL2002 * DUAL CHANNEL NRZI ENCODER / DECODER ^PRELIMINARY PIN CONFIGURATION FEATURES • ■ ■ ■ ■ ■ ■ ■ ■ Two independent Digital Phase Lock Loop circuits Two independent Full Duplex channels NRZI Encoder/Decoder DPLL runs off 16x clock Crystal o rT T L clock inputs for DPLL

manchester

Abstract: rxc 50 NATIONAL DP8390 SL4000 LTAB
Contextual Info: STARLAN INTERFACE SL4000 PRELIMINARY PIN O UT FEATURES - 1 XTAL2- 2 19 - PSEL RXDOUT- 3 18 - RXDIN TXD IN -CTS -CRS - 4 RTS 5 7 -16 -15 -14 - LPBK - 8 13 - CD2 XTAL1 8X CLKIN o INTERFACE FOR THE LAN CONTROLLERS o UP TO 4 MBITS PER SECOND DATA RATE

intel 80286 pin diagram

Abstract: intel 80286 intel i5 8284A clock generator intel 80286 block diagram CHIPset for 80286 SL6001 SL6002 SL600
Contextual Info: PC / AT C O M PA TIBLE C H IP-SET SL600X SL6001/SL6002/SL6003/SL6004/SL6Q05 "^ T INARY \ DESCRIPTION FEATURES • 100% compatible with IBM TM PC AT • Pin-to-pin compatible with Chips & Technology’s chip-set Support 10 MHz with zero Wait State or 12 MHz with one Wait State

Contextual Info: UNIVERSAL PC/AT CLOCK CHIP GICSTAR _SL9090 PRELIMINARY FEATURES • Generates all essential Clock Signals for P.C.'s. • Supports 8086/8088/80286/80386SX/80386-based designs. • Clock Options of 6 0 ,5 0 ,4 8 ,4 0 , or 32 MHz and others.

Contextual Info: UNIVERSAL V IDEO CLOCK CHIP SL9091 GICSTAR PRELIMINARY FEATURES • Generates all essential Clock Signals for Video. • Ideal for all EGA, VGA applications. • Select code is IBM compatible. • Generates 16 different clock frequencies 14 to 55 MHz . • Requires only one Crystal and few RC components.

Contextual Info: PAGE MODE MEMORY CONTROLLER _ SL9250 PRELIMINARY FEATURES • 16 or 20 MHz Options. • Enhanced fast page mode design. • Programmable wait state options. • Shadow Ram feature. • Supports 8 M byte of on board memory. • Can use 256K x 1 ,1 Meg x 1, and 256K x 4 DRAMs or a mix.

74LS612

Abstract: Memory Mapper
Contextual Info: MEMORY MAPPER FOR PC-AT ' SL6012 PRELIMINARY O ^ ' 005146 FEATURES PIN OUT ^ • Expands 4 Address Lines to 8 Address Lines RS VDD 40 2 MA3 MA2 39 RS3 RSI 38 3 • D esign ed for PC / AT Paged Memory M apping • 3-State Map Outputs • H igh Speed Low Power CMOS

paradise ppc1

Contextual Info: Parallel Printer Port Interface ¿9j y '10 Ä 5001 ARY 0v -^ 005147 R, TM • Full IBM PC Parallel Port Compatible • Pin-to-Pin Compatible with Paradise System's PPC1. GND own • High Speed low power CMOS technology SL5001 ININ • 24 mA Sink & -12 mA Source current for

Contextual Info: PC / AT COMPATIBLE CHIP-SET SL600X SL6001/SL6002/SL6003/SL6004/SL6D05 ,-„ —J. , . . IMINARY \ FEATURES DESCRIPTION 100% compatible with IBM TM PC AT Pin-to-pin compatible with Chips & Technology’s chip-set Support 10 MHz with zero Wait State

Contextual Info: SYSTEM CONTROLLER SL9010 GICSTAR PRELIMINARY FEATURES • AT system control logic. • Supports 80386,80386 SX P9 , or 80286-based designs. • 1 6,20,25 MHz options. • Clock switching and reset logic. • Programmable wait states for Memory and I/O. • Programmable command delays for Memory.

386SX

Abstract: 80386-sx buffer SL9010 OPT387 SL901
Contextual Info: SYSTEM CONTROLLER LQGICSTAR _ SL 901° PRELIMINARY FEATURES • AT system control logic. • Supports 80386,80386 SX P9 , or 80286-based designs. • 16,20,25 MHz options. • Clock switching and reset logic. • Programmable wait states for Memory and I/O.