MGTS Search Results

switching power supply design

Abstract: DIODE C18 ph 48v power supply XAPP946 ph c30 diode sot-223 package ph code TPS54110PWP TPS54610 TPS54610PWP TPS73625
Contextual Info: Application Note: Virtex-4 Family R XAPP946 v1.0.1 August 14, 2006 Summary Switching Power Supplies for Virtex-4 RocketIO MGTs Author: Justin Gaither This document presents design techniques and reference circuits that power Virtex -4 FX RocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.

2VP50

Contextual Info: New Products Rocket I/O MGTs Use Rocket I/O Multi-Gigabit Transceivers to Double Your FPGA Bandwidth Virtex-II Pro Platform FPGAs break open the I/O bottleneck. As FPGAs increase in size and performance, I/O resources become the main bottleneck to FPGA performance. Although the effective area of a chip grows as the square of the

TXENC8B10BUSE

Abstract: UG076 XAPP732 MGT 2
Contextual Info: Application Note: Virtex-4 Family of FPGAs Inactive Transceiver Behavior WorkArounds for Virtex-4 FX RocketIO MGTs R XAPP732 v1.1 September 25, 2007 Summary Author: Vinod Venkatavaradan This application note contains detailed information related to the Virtex -4 RocketIO™ MultiGigabit Transceiver (MGT) Static Operating Behavior described in EN014 (Errata for Virtex-4

TRANSISTOR SMD K23

Abstract: B DIN 5463
Contextual Info: User's Guide SLAU296 – October 2009 ADS54RF63-ADX4 Single-channel, 12-bit, 2.2 GSPS Evaluation Module EVM 1 2 3 4 5 6 7 8 9 10 Contents Introduction . 2

XQR4VSX55-10CF1140V

Abstract: XQR4VSX55 CF1140 XQR4VFX140-10CF1509V XQR4VSX55-10CF1140 CF1144 XQR4VFX140-10CF1509 XtremeDSP XQR4VFX60-10CF1144 xqr4vlx200
Contextual Info: R Space-Grade Virtex-4QV Family Overview DS653 v2.0 April 12, 2010 Product Specification General Description The Virtex -4QV family of space-grade, radiation-tolerant FPGAs meets the requirements of space applications that demand high-performance as well as control capabilities. For years, the only solution available to customers with highperformance space applications were ASICs with long development and fabrication times as well as high NREs. Now,

DSP48

Abstract: DSP48A DSP48E DSP48E1 PPC405 PPC440 UG112 iodelay UG440 LX240T
Contextual Info: XPower Estimator User Guide [Guide Subtitle] [optional] UG440 v4.0 May 3, 2010 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

BLVDS-25

Abstract: LVDSEXT-25 4564 RAM XC2VP70 FF1704 pinout XC2V1000 Pin-out XC2V1500 XC2V2000 XC2V3000 XC2V6000 XC2V8000
Contextual Info: Xilinx Virtex-II Series FPGAs and RocketPHY Physical Layer Transceivers Transceiver Blocks 992 88 120 200 264 432 528 624 720 912 1104 1108 Chip Scale Packages CS – wire-bond chip-scale BGA (0.8 mm ball spacing) 144 8 88 92 FF896 92 8 FF1152 BGA Packages (BG) – wire-bond standard BGA (1.27 mm ball spacing)

qfn 3x3 tray dimension

Abstract: XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga
Contextual Info: Device Package User Guide [Guide Subtitle] [optional] UG112 v3.5 November 6, 2009 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

MCA8

Abstract: tube 7586 M350M
Contextual Info: Gas Discharge Tube FEATURE • • • • • • MGT Series UL E223045 Rugged Ceramic-Metal Construction Available With Fail-Safe Clip Available With Or Without Leads Available With Various Lead Spacing Low capacitance < 2pF Large Transient Current Absorbing Capability

Serial RapidIO

Abstract: GT11 RocketIO
Contextual Info: .’ Serial RapidIO Physical Layer v4.1 DS293 February 15, 2007 Product Specification Introduction LogiCORE Facts The LogiCORE Serial RapidIO Physical Layer cores are fixed-netlist solutions for the RapidIO interconnect. The 1x and 4x cores are pre-implemented and fully

XAPP662

Abstract: PPC405 XAPP138 XAPP660 XAPP661 XC2VP20 FF1152 FF672 Virtex-II Platform FPGA Complete All Four Module verilog code of prbs pattern generator
Contextual Info: Application Note: Virtex-II Pro Family R XAPP662 v1.1 July 3, 2003 Summary In-Circuit Partial Reconfiguration of RocketIO Attributes Author: Vince Eck, Punit Kalra, Rick LeBlanc, and Jim McManus This application note describes in-circuit partial reconfiguration of RocketIO transceiver

1000BASE-X

Abstract: vhdl code for defer block coding in mac transmitter verilog code for mdio protocol verilog code for MII phy interface DS200 xip2150 xilinx tcp vhdl
Contextual Info: zozo 1-Gigabit Ethernet MAC Core with PCS/PMA Sublayers 1000BASE-X or GMII v3.0 R DS200 (v1.1) April 30, 2003 Product Specification Features • LogiCORE Facts Single-speed 1-gigabit-per-second Ethernet Media Access Controller (MAC) Core Specifics •

Contextual Info: ` Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.4.1 March 24, 2003 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIO™ embedded

RX-2C G

Abstract: tx2c transmitter TX 2E 1240 picosecond tx-2b equivalent Gigabyte 848 TX-2B RX-2B ROSENBERGER RX_2B XENPAK70
Contextual Info: Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide UG076 v4.1 November 2, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

SMD fuse P110

Abstract: 74c914 transistor b733 transistor SMD p113 EPSON C691 MAIN npn transistor smd w19 smd diode c539 transistor b771 transistor c1015 transistor c1008 011
Contextual Info: 4 3 Figure 1: 2 1 ML300 CPU Table 1: ML300 CPU Virtex-II Pro Based Virtex-II Pro Based Block Diagram Table of Contents D D Infiniband HSSCD2 Dual Gig-E Fiber (Quad) Serial ATA (Dual) Sheet 1: Sheet 2: Sheet 3: Sheet 4: Sheet 5: Sheet 6: Sheet 7: Sheet 8:

AM3 pinout diagram

Abstract: SX35 SX35 virtex XC4VLX25-SF363 AM1 marking FF1148 UG075 The Virtex-4 LC system board K155 AH512
Contextual Info: Virtex-4 FPGA Packaging and Pinout Specification UG075 v3.3 September 19, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

MP21608S221A

Abstract: UG198 FERRITE-220 GTX tile oversampling recovered clock ROSENBERGER verilog code for linear interpolation filter aurora GTX BLM15HB221SN1 gearbox rev maxim DVB
Contextual Info: Virtex-5 FPGA RocketIO GTX Transceiver User Guide UG198 v2.1 November 17, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

XAPP759

Abstract: verilog code for fibre channel 1000BASE-X PPC405 Virtex-II Pro and Virtex-II Pro X Platform FPGAs Xuint32 CPCS BOARD POWER SUPPLY ML323 1000base-x xilinx DS264
Contextual Info: Application Note: Virtex-II Pro Family R Configurable Physical Coding Sublayer Author: Dai Huang, Jack Lo, and Shalin Sheth XAPP759 v1.1 March 4, 2005 Summary This application note describes a Configurable Physical Coding Sublayer (CPCS) reference design that extends the functionality of the Xilinx RocketIO multi-gigabit transceiver (MGT)

2VP4-FG456

Abstract: Reconfiguration JTGC405TCK JTGC405TDI JTGC405TMS PPC405 XAPP660 XC2VP20 XC2VP30 XC2VP40
Contextual Info: Application Note: Virtex-II Pro Family R XAPP660 v2.2 February 4, 2004 Dynamic Reconfiguration of RocketIO MGT Attributes Author: Derek R. Curd Summary This application note describes a pre-engineered design module for Virtex-II Pro devices that enables dynamic reconfiguration of RocketIO™ Multi-Gigabit Transceiver (MGT) attributes.

free verilog code of prbs pattern generator

Abstract: verilog code 16 bit LFSR in PRBS pattern generator lfsr galois prbs using lfsr lfsr fibonacci XAPP661 verilog code for 10 gb ethernet verilog code 8 bit LFSR verilog HDL program to generate PWM
Contextual Info: Application Note: Virtex-II Pro Family R RocketIO Transceiver Bit-Error Rate Tester Author: Dai Huang and Michael Matera XAPP661 v2.0.2 May 24, 2004 Summary This application note describes the implementation of a RocketIO transceiver bit-error rate tester (BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s) between

ug196

Abstract: johnson tiles GTX tile oversampling recovered clock XC5VLX30T-FF323 aurora GTX ROSENBERGER XC5VSX50TFF665 2F-15 UCF virtex-4 BLM15HB221SN1
Contextual Info: Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 v2.0 June 10, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

32K10K-400

Abstract: CP1005 12ah4 CFD06 IOG20 32k10k400 IOG11 12ah3 12AH-4 32K10K
Contextual Info: 4 3 2 1 4 3 2 1 STANDARD CLOCKS D D SOCKET OSC ON BOARD FPGA SUPPLIES 5V Jack OR C 5V Brick OR 5V Brick SMA OSC SMA DIFF MGT MGT MGT MGT 2X2 2X2 2X2 2X2 SMA SMA SMA SMA MGT MGT VCC3 C MGT CLOCKS System Ace MGT POWER MODULE 3.3V 2X2 2X2 2X1 VCORE 2X1 SMA SMA

Contextual Info: Virtex-II Pro Platform FPGAs: Introduction and Overview R DS083-1 v2.3 November 20, 2002 Advance Product Specification Summary of Virtex-II Pro Features • • High-Performance Platform FPGA Solution, Including - Up to twenty-four RocketIO™ embedded

M88E1111

Abstract: 32K10K-400E3 JS28F256P30 W25Q64VSFIG M88E1111 ETHERNET ICS874001 Chrontel CH7301C-TF 32K10K-400 XC6SLX45T-3FGG484 schematic diagram epson r230
Contextual Info: SP605 Hardware User Guide [Guide Subtitle] [optional] UG526 v1.1 November 9, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the