DS614 Search Results

PLL variable frequency generator

Abstract: QPro Virtex 4 Hi-Rel PLL 02A DS614 fpga 3 phase inverter DS6-14 MMCM
Contextual Info: Clock Generator DS614 April 19, 2010 Product Specification Introduction LogiCORE IP Facts Core Specifics The Clock Generator module provides clocks according to system wide clock requirements. Virtex -6/6CX, Spartan®-6, Spartan-3A/3A DSP, Spartan-3, Spartan-3E, Automotive

DIM400XSM45-TS001

Contextual Info: Data DIM400XSM45-TS001 Single Switch IGBT Module Replaces DS6149-1 DS6149-2 August 2014 LN31876 FEATURES KEY PARAMETERS • 10.2kV Isolation  10µs Short Circuit Withstand  High Thermal Cycling Capability VCES VCE(sat) * (typ) IC (max) IC(PK) (max)

DFM1200AXM45-TS001

Contextual Info: DFM1200AXM45-TS001 Fast Recovery Diode Module DS6146-1 April 2014 LN31501 FEATURES KEY PARAMETERS • VRRM VF IF IFM 10.2kV Isolation Package  Low Reverse Recovery Charge  High Switching Speed  Low Forward Volt Drop  Isolated AlSiC Base With AlN Substrates

DCR3640H85

Contextual Info: DCR3640H85 Phase Control Thyristor Preliminary Information DS6140-2 October 2014 LN32030 KEY PARAMETERS FEATURES • Double Side Cooling  High Surge Capability VDRM IT(AV) ITSM dV/dt* dI/dt 8500V 3640A 54000A 2000V/µs 200A/µs * Higher dV/dt selections available

PLL 02A

Abstract: SPARTAN 3an
Contextual Info: Clock Generator v4.03a DS614 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The Clock Generator IP core receives common clock requirements through its parameters and generates architecture-specific clocking circuitry, implemented in

DCM03

Abstract: vhdl code for All Digital PLL vhdl code for DCM vhdl code for phase shift Digital clock MODULE CIRCUIT DIAGRAM dcmi digital clock digital clock vhdl code CLK180 DS614
Contextual Info: Clock Generator DS614 June 24, 2009 Product Specification Introduction LogiCORE Facts The Clock Generator module provides clocks according to system wide clock requirements. Features • Automatic instantiation of Digital Clock Manager DCM modules and their connections

EBR-1553

Abstract: SAE-AS5652 RS485-Bus AS5652 MMSI rta2 DO25 HI-6130 100PQS as565
Contextual Info: HI-6140 10 MBit/s MIL-STD-1553 3.3V BC / MT / RT January 2013 GENERAL DESCRIPTION FEATURES The HI-6140 is a 10 MBit/sec version of Holt’s HI-6130 integrated BC/MT/RT solution. The part is designed for MIL-STD-1553-derived protocols that use a 10MB/sec data rate, such as Miniature Munitions Stores Interface

M88E1111

Abstract: 32K10K-400E3 JS28F256P30 W25Q64VSFIG M88E1111 ETHERNET ICS874001 Chrontel CH7301C-TF 32K10K-400 XC6SLX45T-3FGG484 schematic diagram epson r230
Contextual Info: SP605 Hardware User Guide [Guide Subtitle] [optional] UG526 v1.1 November 9, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

AES17-1991

Abstract: CDB42406 CS42406 CS42406-CQZ CS42406-DQ CS42406-DQZ
Contextual Info: CS42406 24-Bit, 192 kHz 2-In 6-Out Audio CODEC D/A Features A/D Features 24-Bit Conversion 102 dB Dynamic Range at 5 V -91 dB THD+N Digital Volume Control with Soft Ramp 24-Bit Conversion 105 dB Dynamic Range at 5 V -98 dB THD+N Advanced Multi-Bit Delta-Sigma Architecture

Contextual Info: 'I# MODEL 91. m ds-614 SURFACE MOUNT DOUBLEBALANCED MIXER 0.7 - 2 g h z Fully Hermetic Package 6 dB Typical Midband Conversion Loss 25 dB Typical Isolation Guaranteed Specifications* From - 5 5 ° C t o + 8 5 ° C Frequency Range RF, LO Ports IF Port Conversion Loss

alaska atx 250 p4

Abstract: DSP48A1 SP605
Contextual Info: SP605 Hardware User Guide UG526 v1.8 September 24, 2012 Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

AES17-1991

Abstract: CDB42406 CS42406 CS42406-CQZ CS42406-DQZ MS026 4102A
Contextual Info: CS42406 24-Bit, 192 kHz 2-In 6-Out Audio CODEC D/A Features A/D Features 24-Bit Conversion 102 dB Dynamic Range at 5 V -91 dB THD+N Digital Volume Control with Soft Ramp 24-Bit Conversion 105 dB Dynamic Range at 5 V -98 dB THD+N Advanced Multi-Bit Delta-Sigma

Contextual Info: SP623 Spartan-6 FPGA GTP Transceiver Characterization Board User Guide UG751 v1.1 September 15, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

ds6-14f

Contextual Info: DS6-14F Diodes Silicon Rectifier Military/High-RelN I O Max.(A) Output Current10 @Temp (øC) (Test Condition)100# V(RRM)(V) Rep.Pk.Rev. Voltage1.4k I(FSM) Max.(A) Pk.Fwd.Sur.Cur.180 V(FM) Max.(V) Forward Voltage1.6 @I(FM) (A) (Test Condition)30 @Temp. (øC) (Test Condition)25õ

aspi-024-aspi-s402

Abstract: ML510 xilinx mig user interface design VIRTEX-5 DDR2 VIRTEX-5 DDR2 controller virtex ml510 xc5vlx130t ChipScope XAPP778 XPS IIC
Contextual Info: ML510 MIG Design Creation Using ISE 11.1, MIG 3.0 and ChipScope™ Pro 11.1 May 2009 Overview ƒ Hardware Setup ƒ Software Requirements ƒ CORE Generator™ software – Memory Interface Generator MIG ƒ Modify Design – Add ChipScope Pro Cores to Design

Contextual Info: P/N: C-1xx-1250 C -TDFB(3)-SSC2(3/4)x(-G5) 1.25 Gbps CWDM Single Mode Transceiver Features z z z z z z z z z z z z z z SC Duplex Single Mode Transceiver Industry Standard 1x9 Footprint Complies with IEEE 802.3 Gigabit Ethernet Single +3.3V/5V Power Supply

EBR-1553

Abstract: SAE-AS5652 AS5652 HI-6130 IRIG B decoder 6140 HI-6140 100PQS IRIG 106 IRIG Rev 3
Contextual Info: HI-6140 10 MBit/s MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT May 2012 GENERAL DESCRIPTION FEATURES The HI-6140 is a 10 MBit/sec version of Holt’s HI-6130 integrated BC/MT/RT solution. The part is designed for MIL-STD-1553 or MIL-STD-1760 applications using a

XC6SLX16-2CSG324

Abstract: M88E111 28f128j3d75 SPARTAN 6 Configuration XC6SLX16-2 W25Q64 W25Q64VSFIG VITA-57 Marvell PHY 88E1111 errata W25Q64vs
Contextual Info: SP601 Hardware User Guide [Guide Subtitle] [optional] UG518 v1.1 August 19, 2009 [optional] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the

ML505

Abstract: ml507 MT4HTF3264HY-53e VIRTEX-5 DDR2 ps2 controller ML506 aspi-024-aspi-s402 MT4HTF3264HY DS695 VIRTEX-5 DDR2 controller
Contextual Info: ML505/506/507 MIG Design Creation Using ISE 11.1, MIG 3.0 and ChipScope™ Pro 11.1 May 2009 Overview ƒ Hardware Setup ƒ Software Requirements ƒ CORE Generator™ software – Memory Interface Generator MIG ƒ Modify Design – Add ChipScope Pro Cores to Design

aspi-024-aspi-s402

Abstract: DS444 xilinx mig user interface design MT4HTF3264HY-53e VIRTEX-5 DDR2 VIRTEX-5 DDR2 controller XAPP1026 ug086 XPS IIC chipscope manual
Contextual Info: ML501 MIG Design Creation Using ISE 10.1i SP3, MIG 2.3 and ChipScope™ Pro 10.1i November 2008 Overview • Hardware Setup • Software Requirements • CORE Generator™ software – Memory Interface Generator MIG • Modify Design – Add ChipScope Pro Cores to Design

ICS85104

Abstract: marvell ibis 88e1111 South Bridge ALI M1535 ALi M1535D Marvell 88E1111 trace layout guidelines us power supply atx 250w schematic M1535 XAPP925 rtc8564 JS28F256P30T95
Contextual Info: ML510 Embedded Embedded Development Development Platform User Guide [optional] UG356 v1.1 December 11, 2008 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

ML505

Abstract: ML507 XPS IIC ML506 JTAG Xilinx lcd ML506 VIRTEX-5 DDR2 pcb design sata2 design guide VIRTEX-5 DDR PHY ML50x
Contextual Info: ML505/ML506/ML507 ML505/ML506/M L507 Reference Reference Design Design User Guide [optional] UG349 v3.0.1 June 27, 2008 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development

XAPP1041

Abstract: 88E1111 PHY registers map Marvell PHY 88E1111 Datasheet Marvell PHY 88E1111 Xilinx Marvell PHY 88E1111 Xilinx spartan Marvell PHY 88E1111 alaska Marvell PHY 88E1111 alaska register map marvell 88e111 alaska reference design powerpc 405 embedded powerpc 440
Contextual Info: Application Note: Embedded Processing R XAPP1041 v2.0 September 24, 2008 Abstract Reference System: XPS LL Tri-Mode Ethernet MAC Embedded Systems for MicroBlaze and PowerPC Processors Author: Ed Hallett This application note describes three reference systems and outlines how to use the XPS Local

fsp250-60

Abstract: alaska atx 250 p4
Contextual Info: ML510 Embedded Embedded Development Development Platform User Guide [optional] UG356 v1.2 June 16, 2011 [optional] R R Copyright 2008 – 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included