MAX9313 Search Results

Contextual Info: 19-2078; Rev 2; 10/02 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs.

MAX9311

Abstract: MAX9311ECJ MAX9311EGJ MAX9311EHJ MAX9313 MAX9313ECJ MAX9313EGJ MC100EP111 MC100LVEP111
Contextual Info: 19-2078; Rev 2; 10/02 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs.

Contextual Info: 19-2078; Rev 2; 10/02 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers Features The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs.

Contextual Info: 19-2078; Rev 2; 10/02 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs.

Contextual Info: 19-2078; Rev 0; 8/01 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers Features ♦ +2.25V to +3.8V Differential HSTL/LVPECL Operation ♦ -2.25V to -3.8V LVECL Operation ♦ 30ps typ Part-to-Part Skew ♦ 12ps (typ) Output-to-Output Skew ♦ 312ps (typ) Propagation Delay

Contextual Info: 19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

marking code E5 SMD ic sot23-5

Abstract: Satellite DISEQC SWITCH 4x1 acer laptop motherboard circuit diagram acer laptop battery pinout nec tokin oe 128 schematic LG TV lcd backlight inverter ACER laptop schematic diagram HP COMPAQ MOTHERBOARD CIRCUIT diagram schematic acer lcd backlight inverter APC 5kv UPS CIRCUIT DIAGRAM
Contextual Info: We hope that you will find this CD-ROM a helpful tool for selecting the best Maxim IC for your design. To the left, please find a menu of the documents contained on this CD-ROM. Click on each item for a more detailed list. All of the indexes, tables, and trees on this CD-ROM contain links to product data sheets. After you have viewed a

INSSTE32882

Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B
Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer

maxim MAX9322ECY D

Contextual Info: 19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

CYPRESS SEMICONDUCTOR

Abstract: nxp Cross-reference AMI Semiconductor DSP ICS9112-17 PIC182 C9850 CDCLVD110 IDT CROSS MC100LVE111 MC100LVEP111
Contextual Info: PIN-PIN Compatible Cross-Reference Guide Competitor Name AMI Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK
Contextual Info: 19-2544; Rev 0; 7/02 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver Applications Features ♦ 1.2ps RMS Maximum Random Jitter ♦ 300mV Differential Output at 1.0GHz ♦ 900ps Propagation Delay ♦ Selectable Divide-by-1 or Divide-by-2 Frequency

INSSTE32882

Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877
Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer

Contextual Info: 19-2078; Rev 1; 2/02 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers Both devices are offered in space-saving, 32-pin 5mm ✕ 5mm TQFP, 5mm x 5mm QFN, and industry-standard 32-pin 7mm x 7mm LQFP packages. Applications Precision Clock Distribution

MAX9312

Abstract: MAX9313 MAX9314 MC100LVEP111 TAJB106K010R 293D106X9016B2T MAX9311 MAX9311EVKIT
Contextual Info: 19-2186; Rev 0; 10/01 MAX9311 Evaluation Kit The MAX9311 evaluation kit EV kit includes the MAX9311 low-skew, 1-to-10 differential driver designed for clock distribution. The MAX9311 EV kit supports LVECL/LVPECL testing up to 3GHz. The kit allows selection of two sources and reproduces the selected

MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK 36CW
Contextual Info: 19-2544; Rev 1; 12/02 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

Contextual Info: 19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK
Contextual Info: 19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

JESD86

Abstract: JESD8-6 HSTL standards MAX9310 MAX9311 MAX9312 MAX9313 MAX9314 MAX9315 MAX9316
Contextual Info: Maxim > App Notes > COMMUNICATIONS CIRCUITS Keywords: HSTL, PECL, high speed, interface standards, differential HSTL, high speed transceiver logic, Jedec standard, Jedec std, differential Sep 27, 2002 APPLICATION NOTE 1752 Applying HSTL Signals to PECL Input Devices