MAX9316 Search Results

Contextual Info: 19-2648; Rev 0; 10/02 KIT ATION EVALU E L B AVAILA 1:5 Differential LV PECL/(LV)ECL/ HSTL Clock and Data Driver The MAX9316A is a low-skew, 1-to-5 differential driver designed for clock and data distribution. This device allows selection between two inputs: one differential

MAX9316A

Abstract: MAX9316AEWP MC100EL14
Contextual Info: 19-2648; Rev 0; 10/02 KIT ATION EVALU E L B AVAILA 1:5 Differential LV PECL/(LV)ECL/ HSTL Clock and Data Driver The MAX9316A is a low-skew, 1-to-5 differential driver designed for clock and data distribution. This device allows selection between two inputs: one differential

Contextual Info: 19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

MAX9316

Abstract: MAX9316EUP MAX9316EWP MC100LVEL14
Contextual Info: 19-2237; Rev 0; 10/01 KIT ATION EVALU E L B AVAILA 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features ♦ Guaranteed 400mV Differential Output at 1.5GHz ♦ Selectable Single-Ended or Differential Input ♦ 130ps max Part-to-Part Skew at +25°C

sma-2 package

Abstract: GRM39X7R104K016AD MAX9315 MAX9315EVKIT MAX9316 MAX9316EUP T494B106K010AS TAJB106K010R EMK107BJ104KA GRM36X7R103K016AD
Contextual Info: 19-2280; Rev 0; 1/02 MAX9315 Evaluation Kit Features ♦ Controlled 50Ω Microstrip Traces ♦ Input Trace Lengths Matched to <2mils ♦ Output Trace Lengths Matched to <1mil ♦ Board Frequency: Up to 1.5GHz ♦ 2.375V VCC - VEE Supply Voltage ♦ 20-Pin TSSOP Package

maxim MAX9322ECY D

Contextual Info: 19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

Contextual Info: 19-2237; Rev 0; 10/01 KIT ATION EVALU E L B AVAILA 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features ♦ Guaranteed 400mV Differential Output at 1.5GHz ♦ Selectable Single-Ended or Differential Input ♦ 130ps max Part-to-Part Skew at +25°C

MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK
Contextual Info: 19-2544; Rev 0; 7/02 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver Applications Features ♦ 1.2ps RMS Maximum Random Jitter ♦ 300mV Differential Output at 1.0GHz ♦ 900ps Propagation Delay ♦ Selectable Divide-by-1 or Divide-by-2 Frequency

AN1916

Abstract: MAX9386 MAX9310 MAX9311 MAX9315 MAX9316 MAX9317 MAX9320 MAX9322 MAX9360
Contextual Info: Maxim > App Notes > HIGH-SPEED INTERCONNECT Keywords: jitter, gaussian, random, RJ, deterministic, cycle to cycle, adjacent cycle, duty cycle distortion, pulse width distortion, inter-symbol, bit error rate, BER, ber Mar 06, 2003 APPLICATION NOTE 1916 An Introduction to Jitter in Communications Systems

MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK 36CW
Contextual Info: 19-2544; Rev 1; 12/02 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

Contextual Info: 19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

MAX9316

Abstract: MAX9322 MAX9322ECY MAX9322ETK
Contextual Info: 19-2544; Rev 2; 2/07 LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from

JESD86

Abstract: JESD8-6 HSTL standards MAX9310 MAX9311 MAX9312 MAX9313 MAX9314 MAX9315 MAX9316
Contextual Info: Maxim > App Notes > COMMUNICATIONS CIRCUITS Keywords: HSTL, PECL, high speed, interface standards, differential HSTL, high speed transceiver logic, Jedec standard, Jedec std, differential Sep 27, 2002 APPLICATION NOTE 1752 Applying HSTL Signals to PECL Input Devices