MAX9315 Search Results

Contextual Info: 19-2220; Rev 1; 11/04 KIT ATION EVALU LE B A IL A AV 1 :5 Diffe re nt ia l LV PECL/LV ECL/H ST L Cloc k a nd Da t a Drive r Fe a t ure s The MAX9315 low-skew, 1-to-5 differential driver is designed for clock and data distribution. This device allows selection between two inputs. The selected input

sma-2 package

Abstract: GRM39X7R104K016AD MAX9315 MAX9315EVKIT MAX9316 MAX9316EUP T494B106K010AS TAJB106K010R EMK107BJ104KA GRM36X7R103K016AD
Contextual Info: 19-2280; Rev 0; 1/02 MAX9315 Evaluation Kit Features ♦ Controlled 50Ω Microstrip Traces ♦ Input Trace Lengths Matched to <2mils ♦ Output Trace Lengths Matched to <1mil ♦ Board Frequency: Up to 1.5GHz ♦ 2.375V VCC - VEE Supply Voltage ♦ 20-Pin TSSOP Package

MAX9315

Abstract: MAX9315EUP MC100LVEP14
Contextual Info: 19-2220; Rev 1; 11/04 KIT ATION EVALU LE B A IL A AV 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver The MAX9315 low-skew, 1-to-5 differential driver is designed for clock and data distribution. This device allows selection between two inputs. The selected input

HDMI to vga pinout

Abstract: MAX9180 lvds 26 pin MAX9259 MAX9374 MAX9384 Video sync splitter vga SK4401 HDMI to VGA Cable diagram MAX9324
Contextual Info: High-Speed Interconnect 8th Edition February 2009 Industry’s most versatile portfolio of high-speed interface ICs Automotive SerDes for video and audio data Rear-Seat Entertainment Navigation Safety Cameras Fanout buffers, muxes, and crosspoint switches for clock and data distribution

max14574

Abstract: MAX1786 MAX1788 MAX8899 DS1849 MAX16908 MAX4967 DS3610 max17018 max13487
Contextual Info: Monitor Reports by Product: 1. Find the product of interest in the table below. Note the process and/or package for that product. 2. Use the "Back" button to return to the home page. 3. Select the process in the "Process Reliability" for the product of interest.

Contextual Info: 19-2220; Rev 0; 10/01 KIT ATION EVALU E L B A AVAIL 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features ♦ +2.375V to +3.8V Supply for Differential HSTL/LVPECL Operation ♦ -2.375V to -3.8V Supply for Differential LVECL Operation ♦ Two Selectable Differential Inputs

MAX9315

Abstract: MAX9315EUP MC100LVEP14
Contextual Info: 19-2220; Rev 0; 10/01 KIT ATION EVALU E L B A AVAIL 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver Features ♦ +2.375V to +3.8V Supply for Differential HSTL/LVPECL Operation ♦ -2.375V to -3.8V Supply for Differential LVECL Operation ♦ Two Selectable Differential Inputs

AN1916

Abstract: MAX9386 MAX9310 MAX9311 MAX9315 MAX9316 MAX9317 MAX9320 MAX9322 MAX9360
Contextual Info: Maxim > App Notes > HIGH-SPEED INTERCONNECT Keywords: jitter, gaussian, random, RJ, deterministic, cycle to cycle, adjacent cycle, duty cycle distortion, pulse width distortion, inter-symbol, bit error rate, BER, ber Mar 06, 2003 APPLICATION NOTE 1916 An Introduction to Jitter in Communications Systems

max9263

Abstract: MAX9259 MAX9234 DS90CR216 MAX9268 1280x480 MAX9150 max9234 MAX9257 Automotive LVDS connector LVDS 51 connector
Contextual Info: High-Speed Interconnect Product Guide Learn more Page 3mm x 3mm serializer for miniature security Gigabit, multiport, LVDS crosspoint switches minimize system

JESD86

Abstract: JESD8-6 HSTL standards MAX9310 MAX9311 MAX9312 MAX9313 MAX9314 MAX9315 MAX9316
Contextual Info: Maxim > App Notes > COMMUNICATIONS CIRCUITS Keywords: HSTL, PECL, high speed, interface standards, differential HSTL, high speed transceiver logic, Jedec standard, Jedec std, differential Sep 27, 2002 APPLICATION NOTE 1752 Applying HSTL Signals to PECL Input Devices