5X5X01 Search Results

Contextual Info: 19-2078; Rev 2; 10/02 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs.

Contextual Info: 19-2078; Rev 0; 8/01 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers Features ♦ +2.25V to +3.8V Differential HSTL/LVPECL Operation ♦ -2.25V to -3.8V LVECL Operation ♦ 30ps typ Part-to-Part Skew ♦ 12ps (typ) Output-to-Output Skew ♦ 312ps (typ) Propagation Delay

Contextual Info: 19-1745; Rev 2; 4/04 KIT ATION EVALU E L B AVAILA 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference ♦ Excellent Dynamic Performance 59.5dB SNR at fIN = 20MHz 74dBc SFDR at fIN = 20MHz ♦ Low Power 19mA Normal Operation 5µA (Shutdown Mode) ♦ Fully Differential Analog Input

Contextual Info: 19-2829; Rev 1; 7/03 Anything-to-LVDS Dual 2 x 2 Crosspoint Switches Ordering Information TEMP RANGE PIN-PACKAGE MAX9390EHJ PART -40°C to +85°C 32 TQFP MAX9390ETJ* -40°C to +85°C 32 Thin QFN MAX9391EHJ -40°C to +85°C 32 TQFP MAX9391ETJ* -40°C to +85°C

dvd supply with mosfet dm 100

Abstract: MAX1800EVKIT MAX1801 MAX1800 MAX1800EHJ
Contextual Info: 19-1833; Rev 0; 10/00 KIT ATION EVALU E L B AVAILA Digital Camera Step-Up Power Supply Features ♦ +0.7V to +5.5V Input Voltage Range ♦ Main DC-DC Converter 95% Efficiency +2.7V to +5.5V Adjustable Output Voltage 1.5A Load Current ♦ Uncommitted Gain Block for Linear Regulator

Contextual Info: 19-2688; Rev 0; 1/03 Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers Features ♦ 310ps Propagation Delay Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip reference output VBB1, VBB2 ,

Contextual Info: 19-0736; Rev 0; 1/07 2:1 Multiplexer and 1:2 Demultiplexer with Loopback Features The MAX9396 consists of a 2:1 multiplexer and a 1:2 demultiplexer with loopback. The multiplexer section channel B accepts two differential inputs and generates a single differential output. The demultiplexer section (channel A) accepts a single differential input and

Contextual Info: 19-3953; Rev 3; 7/07 KIT ATION EVALU E L B AVAILA USB Peripheral/Host Controller with SPI Interface The MAX3421E USB peripheral/host controller contains the digital logic and analog circuitry necessary to implement a full-speed USB peripheral or a full-/lowspeed host compliant to USB specification rev 2.0. A

Contextual Info: 19-2287; Rev 0; 1/02 Quad Bus LVDS Transceiver The MAX9157’s high-impedance I/Os except for receiver outputs when VCC = 0 or open, combined with glitch-free power-up and power-down, allow hot swapping of cards in multicard bus systems; 7.2pF (max) BLVDS I/O capacitances minimize bus loading.

Contextual Info: 19-2285; Rev 0; 1/02 Quad Differential LVECL-to-LVPECL Translators The four channels can be operated synchronously with an external clock, or in asynchronous mode, determined by the state of the SEL input. An enable input provides the ability to force all the outputs to a differential low state.

Contextual Info: 19-2390; Rev 0; 4/02 Lowest Jitter Quad PECL-to-ECL Differential Translators The MAX9424–MAX9427 high-speed, low-skew quad PECL-to-ECL translators are designed for high-speed data and clock driver applications. These devices feature an ultra-low 0.24ps RMS random jitter and channel-tochannel skew is less than 90ps in asynchronous mode.

MAX3664

Abstract: MAX3675 MAX3675ECJ MAX3675EHJ
Contextual Info: 19-1258; Rev 4; 4/05 NUAL KIT MA ATION U L A E V E BL AVAILA 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Features ♦ Single +3.3V or +5.0V Power Supply ♦ Complies with ANSI, ITU, and Bellcore SDH/SONET Specifications

MAX9424

Abstract: MAX9425 MAX9426 MAX9427 SK4426 SK4430 SK4436 SK4440
Contextual Info: 19-2390; Rev 0; 4/02 Lowest Jitter Quad PECL-to-ECL Differential Translators The MAX9424–MAX9427 high-speed, low-skew quad PECL-to-ECL translators are designed for high-speed data and clock driver applications. These devices feature an ultra-low 0.24ps RMS random jitter and channel-tochannel skew is less than 90ps in asynchronous mode.

MAX9400

Abstract: MAX9400EGJ MAX9400EHJ MAX9402 MAX9402EHJ MAX9403 MAX9405
Contextual Info: 19-2223; Rev 1; 1/02 Quad Differential LVECL/LVPECL Buffer/Receivers These devices operate with a supply voltage of VCC VEE = 2.375V to 5.5V, and are specified for operation from -40°C to +85°C. These devices are offered in space-saving 32-pin 5mm ✕ 5mm TQFP and 32-lead

MAX9311

Abstract: MAX9311ECJ MAX9311EGJ MAX9311EHJ MAX9313 MAX9313ECJ MAX9313EGJ MC100EP111 MC100LVEP111
Contextual Info: 19-2078; Rev 2; 10/02 1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs.

MAX3421E

Abstract: R20 marking MAX3420E MAX3421EEHJ MAX3421EETG MAX4789 MAX4793 MAX6349TL 12Mhz quartz crystal oscillator
Contextual Info: 19-3953; Rev 0; 2/06 USB Peripheral/Host Controller with SPI Interface The MAX3421E USB peripheral/host controller contains the digital logic and analog circuitry necessary to implement a full-speed USB peripheral or a full-/lowspeed host compliant to USB specification rev 2.0. A

Contextual Info: 19-1729; Rev 2; 4/04 KIT ATION EVALU LE B A IL A AV 10-Bit, 60Msps, 3.0V, Low-Power ADC with Internal Reference The MAX1446 10-bit, 3V analog-to-digital converter ADC features a fully differential input, a pipelined 10stage ADC architecture with digital error correction and

Contextual Info: 19-2223; Rev 2; 1/05 Quad Differential LVECL/LVPECL Buffer/Receivers Features The MAX9400/MAX9402/MAX9403/MAX9405 are extremely fast, low-skew quad LVECL/ECL or LVPECL/ PECL buffer/receivers designed for high-speed data and clock driver applications. These devices feature an

Contextual Info: 19-2913; Rev 0; 8/03 Anything-to-LVDS Dual 2 x 2 Crosspoint Switches Also see the MAX9390/MAX9391 for the crossflow version. Ordering Information TEMP RANGE PIN-PACKAGE MAX9392EHJ PART -40°C to +85°C 32 TQFP MAX9392ETJ* -40°C to +85°C 32 Thin QFN MAX9393EHJ

Contextual Info: 19-5400; Rev 1; 4/04 KIT ATION EVALU E L B A IL AVA 10-Bit, 80Msps, Single 3.0V, Low-Power ADC with Internal Reference The MAX1448 3V, 10-bit analog-to-digital converter ADC features a fully differential input, a pipelined 10stage ADC architecture with wideband track-and-hold

dl321

Abstract: CMSD-4448 MAX1802EVKIT CMSD4448
Contextual Info: 19-1850; Rev 0; 10/00 Digital Camera Step-Down Power Supply The main step-down DC-DC controller accepts inputs from 2.5V to 11V and regulates a resistor-adjustable output from 2.7V to 5.5V. It uses a synchronous rectifier to regulate the output with up to 94% efficiency. An

MAX3664

Abstract: MAX3675 MAX3675ECJ MAX3675EHJ
Contextual Info: 19-1258; Rev 3; 1/00 ANUAL N KIT M IO T A U EVAL BLE AVAILA 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Features ♦ Single +3.3V or +5.0V Power Supply ♦ Complies with ANSI, ITU, and Bellcore SDH/SONET Specifications

MAX9173

Abstract: MAX9390 MAX9390EHJ MAX9391 MAX9391EHJ
Contextual Info: 19-2829; Rev 2; 5/07 KIT ATION EVALU E L B A AVAIL Anything-to-LVDS Dual 2 x 2 Crosspoint Switches Also refer to the MAX9392/MAX9393 with flow-through pinout. Applications High-Speed Telecom/Datacom Equipment High-Level Input Fail-Safe Detection MAX9390

RIN36

Abstract: MAX9129 MAX9157 MAX9157EGJ MAX9157EHJ RE12 RE34
Contextual Info: 19-2287; Rev 0; 1/02 Quad Bus LVDS Transceiver The MAX9157’s high-impedance I/Os except for receiver outputs when VCC = 0 or open, combined with glitch-free power-up and power-down, allow hot swapping of cards in multicard bus systems; 7.2pF (max) BLVDS I/O capacitances minimize bus loading.