M777 Search Results

Contextual Info: Customer Information Sheet I I Œ3 D R A W I N G N o . : M 7 7 6 5 / 6 6 / 6 7 / 7 I-XX S H E E T 2 OF 2 IF IN D O U B T - ASK NOT TO S C A LE THIRD ANGLE P ROJ ECTION ALL D I M E N S I O N S IN m m SPECIFICATIONS: MATERIAL: M OUL DIN G = G LA SS F ILLED PO LYES TER UL94V-0

Contextual Info: TOSHIBA T H M Y 2 5 N 1 1B70f75f80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 33,554,432-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY25N11B is a 33,554,432-word by 64-bit synchronous dynamic RAM module consisting of eight TC59SM808BFT DRAMs and an unbuffer on a printed circuit board.

ic ac 1501-12

Abstract: V53C664K10
Contextual Info: JUN i V 2 1982 PR ELIM IN A R Y V53C664 6 4 K x 16 B IT F A S T P A G E M O D E B YTE W RITE C M OS D YN A M IC R AM VITELIC 80/80L 10/10L Max. RAS Access Time, tRAC 80 ns 100 ns Max. Column Address Access Time, (tCAA) 45 ns 55 ns Min. Fast Page Mode Cycle Time, (tp c )

j477

Abstract: V54C365164VC
Contextual Info: M O S E L V IT E L IC V54C365164VC HIGH PERFORMANCE 143/133/125 MHz 3.3 V 0 L T 4 M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143 MHz 133 MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3

TC59SM716FT

Contextual Info: TO SH IBA THMY648091 EG-80#-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 8,388,608-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY648091EG is a 8,388,608-word by 64-bit synchronous dynamic RAM module consisting of four TC59SM716FT DRAMs and an unbuffer on a printed circuit board.

Contextual Info: NE W! Surface Mount, Micro-Miniature Power Splitter/Combiner 2 Way-0°, 50Ω, SBTC-2-20 patent pending 200 to 2000 MHz Maximum Ratings Features Operating Temperature -40°C to 85°C Storage Temperature -55°C to 100°C Power Input (as a splitter) 0.5W max.

Contextual Info: MOSEL- VITELIC V52C4256 MULTIPORT VIDEO RAM WITH 256K X 4 DRAM AND 5 1 2 X 4 SAM HIGH PERFORMANCE V52C4256 60 PRELIMINARY 80 10 70 ns 80 ns 100 ns 20 ns 25 ns 25 ns 40 ns 50 ns 70 Max. RAS Access Time, tp^c 60 ns Max. CAS Access Time, <tQAC) 15 ns Max. Column Address Access Time, (tAA)

rca thyristor manual

Abstract: HN623258 101490
Contextual Info: Quick Reference Guide to Hitachi 1C Memories Package Information Reliability of Hitachi 1C Memories Applications MOS Static RAM MOS Pseudo Static RAM Application Specific Memory MOS Dynamic RAM MOS Dynamic RAM Module MOS Mask ROM MOS PROM ECL RAM P> Jc^< j

920c5

Abstract: HY6264A-10 HY6264A 4A-10 HY6264A-12 HY6264A-15 HY6264A-70 HY6264A-85 C0553
Contextual Info: HYUNDA SEMICONDUCTO 8KX 8-Bit CMOS SRAM M261201B-MAY92 DESCRIPTION FEATURES The H Y6264A is a high speed, low power 8,192 words by 8-bit CMOS static RAM fabrica­ ted using a twin tub CMOS process technolo­ gy. This high reliability process coupled with innovative circuit design techniques, yields

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿¿P D 4 3 1 0 1 6 L 1 M-BIT CMOS FAST STATIC RAM 64 K-WORD BY 16-BIT Description The /iPD431016L is a high speed, low power, 1, 048, 576 bits 65, 536 words by 16 bits CMOS static RAM, Operating supply voltage is 3.3 V ± 0.3 V.

M20-9890222

Contextual Info: 0 2 5 Connector S p ecification Electrical Current rating: Contact resistance: Insulation resistance: Voltage Proof: Capacitance: M aterials 3 Amps 15 Milliohms 1 xl0 6 Megohms at 500 V d.c. 750 V rms at 50 Hz 1.5 pF Housing: Socket Contacts: Plug contacts:

sl6se

Abstract: SL6B8 M78XX M72 7 segment m72 seven segment Micro Sensor clts sl5lg ptc m71 seven segment m74 intel ia 32
Contextual Info: R Mobile Intel Celeron® Processor 0.18µ and 0.13µ Specification Update November 2006 Version 054 Notice: The mobile Intel® Celeron® processor (0.18µ and 0.13µ) may contain design defects or errors known as errata which may cause the product to deviate from published

tca 785 application

Abstract: TCA 785 application note 102h cbe 001H 101H 200H PM7346 yl 223h relay
Contextual Info: PM7346 S/UNI-QJET PRELIMINARY DATA SHEET PMC-960835 ISSUE 4 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3 PM7346 TM S/UNI- QJET S/UNI-QJET SATURN QUAD USER NETWORK INTERFACE FOR J2/E3/T3 DATA SHEET PRELIMINARY ISSUE 4: JANUARY 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA., INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Contextual Info: HM5241605C Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM HITACHI A D E - 2 0 3 - 1 8 6 A Z R e v . 1 .0 M ay. 22, 1996 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2

Nippon capacitors

Contextual Info: HB526A264DB Series 1,048,576-word x 64-bit x 2-bank Synchronous Dynamic RAM Module HITACHI ADE-203-607 Z Preliminary Rev. 0.1 May. 20, 1997 Description The HB526A264DB is a lM x 64 x 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O .D IM M ), mounted 8 pieces of 16-Mbit SD RAM (HM5216805TT/HM5216805LTT) sealed in

Contextual Info: TO SH IBA THMY12N11B70f75f80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY12N11B is a 16,777,216-word by 64-bit synchronous dynamic RAM module consisting of four TC59SM816BFT DRAMs and an unbuffer on a printed circuit board.

LT 7215

Abstract: M77XX-XX LT 542 C003XX
Contextual Info: Customer information Sheet DRAWING No.: M 7 7 6 5 / 6 6 /6 7 / 7 1 -X X S H E E T 2 OF 2 | IF IN DOUBT - ASK | 1 @ NOT TO S C A L E | THIRD ANGLE PROJECTION A L L DIMENSIONS IN mm SPECIFICATION: MATERIAL: MOULDING - PO LYESTER U L 9 4 V -0 SEE ORDER CODE FOR COLOUR

RMS-25MHW

Contextual Info: NE W! Surface Mount Frequency Mixer Level 13 LO Power +13 dBm Maximum Ratings RMS-25MHW 5 to 2500 MHz Features Operating Temperature -40°C to 85°C Storage Temperature -55°C to 100°C RF Power 200mW IF Current 40mA • low conversion loss, 7.0 dB typ.

HM534

Abstract: hitachi sr 302 HM53462P-12 HM53462P12 HM53462P-15
Contextual Info: HMS3462 Series 65,536-word x 4 bits Multi Port DRAM with Logic operation mode The HM53462P is a 262,144 bit multi port memory equipped with a 64k word x 4 bit Dynamic RAM port and a 256 word x 4 bit Serial Access Memory (SAM) port. The SAM port is con­

W777777

Contextual Info: JUN 1 2 1992 Ijr‘ VITEUC V52C8128 MULTIPORT VIDEO RAM WITH 128KX8 DRAM AND 256 X 8 SAM HIGH PERFORMANCE V52C8128 80 10 Max. RAS Access Time, tRAc 80 ns 100 ns Max. CAS Access Time, (tcAc) 25 ns 25 ns Max. Column Address Access Time, (t^ ) 45 ns 50 ns Min. Fast Page Mode Cycle Time, (tpc)

Contextual Info: M OSEL VITELIC V54C365164VB HIGH PERFORMANCE 143/133/125 MHz 3.3 V 0 L T 4 M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 7 75 8PC 8 System Frequency fCK 143 MHz 133 MHz 125 MHz 125 MHz Clock Cycle Tim e (tcK 3 ) 7 ns 7.5 ns 8 ns 8 ns Clock Access Tim e (tAC3) CAS Latency = 3

ic ac 1501-12

Abstract: V53C664K10 DN-19 MCSI
Contextual Info: JUN i V 2 1982 PR ELIM IN A R Y V53C664 6 4 K x 16 B IT F A S T P A G E M O D E B YTE W RITE C M OS D YN A M IC R AM VITELIC 80/80L 10/10L Max. RAS Access Time, tRAC 80 ns 100 ns Max. Column Address Access Time, (tCAA) 45 ns 55 ns Min. Fast Page Mode Cycle Time, (tp c )

max 7765

Contextual Info: DRAWING No,i- M 7765/66/67/71-X X SHEET 2 OF 2 | IF IN DOUBT - ASK | NOT TO SCA LE | THIRD ANGLE PROJECTION_ | A L L DIMENSIONS IN mm CU STOM ER INFORMATION S H E E T DATAi INSERTION FORCE: MAX, 4N PER PIN 8N PER PAIR, SEPARATING FORCE: MIN, 0.5N PER PIN

TC59SM816BFT

Abstract: THMY12N11B70 EE4H
Contextual Info: TO SH IBA THMY12N11B70f75f80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 16,777,216-WORD BY 64-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY12N11B is a 16,777,216-word by 64-bit synchronous dynamic RAM module consisting of four TC59SM816BFT DRAMs and an unbuffer on a printed circuit board.