INTEL 80960 PIPELINE ARCHITECTURE Search Results

80960MC

Abstract: INTEL 80960 pipeline architecture M82965 80960
Contextual Info: Introduction to the 80960 Architecture 2 CHAPTER 2 INTRODUCTION TO THE 80960 ARCHITECTURE This chapter provides an overview of the architecture on which the 80960MC processor is based. A NEW 32-BIT ARCHITECTURE FROM INTEL The 80960MC processor is the military-grade member of a new family of processors from

M82965

Contextual Info: 80960MC PRODUCT OVERVIEW This chapter provides an overview o f the architecture o f the 80960M C processor. The 80960M C processor is the m ilitary-grade m em ber o f a new fam ily o f processors from Intel. This processor family is based on a new 32-bit architecture called the 80960 architecture. The

a6059

Abstract: a6060 pin diagram of intel dual core processor semiconductor A6060 A6060-01 32-bit microprocessor architecture 80960Rm addressing modes of dual core processor clock generator in dual core processor 80960JT
Contextual Info: Introduction 1.1 1 Intel’s i960 RM/RN I/O Processor The i960 RM/RN I/O processor integrates a high-performance 80960 “core” into a Peripheral Components Interconnect PCI functionality. This integrated processor addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. As indicated in

branch conditional unconditional instruction

Abstract: 80960CF Intel 960
Contextual Info: 80960CF-40, -33, -25, -16 1.0 PURPOSE 2.0 This document provides electrical characteristics of Intel's ¡960 CF embedded microprocessor. For functional descriptions consult the /'960® Cx Micro­ processor User’s Manual 270710 . To obtain data sheet updates and errata, contact Intel at any of the

Date Code Formats intel

Abstract: 80960 Programmer Reference manual 80960MC 80960 Reference Manual
Contextual Info: Guide to this Manual 1 CHAPTER 1 GUIDE TO THIS MANUAL This chapter describes the organization o f this m anual, the contents o f each chapter, and term inology used in the manual. It also outlines the chapters o f the manual that are o f m ost interest to applications program m ers, com piler designers, and designers of operating-system

Contextual Info: 3.3 V 80960JA/JF 1.0 PURPOSE This docum ent contains inform ation for the 80960JA/JF microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions — other than para­ m etric perform ance — are published in the i96 P Jx

Contextual Info: 80960JD 1.0 PURPOSE This document contains advance inform ation for the 80960JD microprocessor, including electrical characteristics and package pinout information. Detailed functional descriptions — other than param etric perform ance — are published in the

i486 sx

Abstract: 80960CX 80960JF 80960RD 80960RP 272736 272918 INTEL386 pipeline architecture
Contextual Info: Intel i960® RX I/O Processor at 3.3 Volts Datasheet • 33 MHz, 3.3 Volt Version 80960RP 33/3.3 • 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core • Complies with PCI Local Bus Specification, Revision 2.1 • 5 Volt PCI Signalling Environment

Intel i960 VH Embedded-PCI Processor Provides Integrated Memory Control and PCI Bus Interface

Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-M apped Data Cache — Sixteen 32-Bit Global Registers

80960Cx

Abstract: PCI80960 80960JF 80960RP i960RP
Contextual Info: Intel i960® RP I/O Processor Datasheet • 33 MHz, 5 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification, Revision 2.1 Product Features • ■ ■ ■ ■ High Performance 80960JF Core —Sustained One Instruction/Clock Execution

8096 processor architecture

Contextual Info: intei 1.0 8 0 9 6 0 H A/H D / H T This docum ent provides a preview of Intel’s 80960Hx embedded superscalar microprocessors. Future revisions of this docum ent will provide targeted electrical characteristics. Detailed descriptions for functional topics — other than param etric perfor­

80960JT

Abstract: 80960VH AD10 MA11 273179
Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

80960JT

Abstract: 80960VH AD10 MA11
Contextual Info: i960 VH Embedded-PCI Processor Advance Information Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

A10 bga

Abstract: intel flash memory W18 80960JT 80960VH AD10 MA11
Contextual Info: i960 VH Embedded-PCI Processor Preliminary Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

80960VH

Abstract: INTEL DX2 80960JT AD10 MA11 cc5r
Contextual Info: i960 VH Embedded-PCI Processor Preliminary Datasheet Product Features • ■ ■ ■ High Performance 80960JT Core — Sustained One Instruction/Clock Execution — 16 Kbyte Two-Way Set-Associative Instruction Cache — 4 Kbyte Direct-Mapped Data Cache

Contextual Info: ADVANCE INFORMATION ¡960 RP/RD I/O PROCESSOR AT 3.3 VOLTS 33 MHz, 3.3 Volt Version 80960RP 33/3.3 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960J F Core • Complies with PCI Local Bus Specification Revision 2.1 • 5 Volt P C I Signalling Environment

272737

Abstract: 80960JF 80960RD 80960RP AD10 AD11 MA11 27248
Contextual Info: ADVANCE INFORMATION i960 RP/RD I/O PROCESSOR AT 3.3 VOLTS • • • • 33 MHz, 3.3 Volt Version 80960RP 33/3.3 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core Complies with PCI Local Bus Specification Revision 2.1 5 Volt PCI Signalling Environment

Contextual Info: Ä I D W M C S Ö M F @ [^ M Ä ?D [K 1 ir tU October 1989 3 80960CA Product Overview 32-Bit High-Performance Embedded Processor with On-Chip DMA Controller, Interrupt Controller, High-Speed Bus Unit, Instruction and Register Caches Order Number: 270669-001

chromerics

Abstract: OV26 80960JF 80960RP AD10 AD11 MA11 272736 27248 i960RP
Contextual Info: ADVANCE INFORMATION i960 RP I/O PROCESSOR • 33 MHz, 5.0 Volt Version 80960RP 33/5.0 • Complies with PCI Local Bus Specification Revision 2.1 • High Performance 80960JF Core ■ ■ ■ ■ ■ DMA Controller — Sustained One Instruction/Clock Execution

80960MC

Abstract: processor cross reference INTEL 80960 pipeline architecture
Contextual Info: Introduction to the 80960MC Microprocessor CHAPTER 1 INTRODUCTION TO THE 80960MC MICROPROCESSOR The 80960MC is the military version of the 80960 family, designed especially for high reliability embedded applications. At an operating frequency of 20 MHz, this high performance processor can

272737

Abstract: 80960JF
Contextual Info: IP[n3 [ [!J©T [PGiEWOG in te i 80960RP INTELLIGENT I/O MICROPROCESSOR • ■ PCI-to-PCI BRIDGE UNIT HIGH PERFORMANCE 80960JF CORE — Primary and Secondary PCI Interfaces — Sustained One Instruction/Clock — Two 64-Byte Posting Buffers Execution — Supports Delayed and Posted

80960SA

Abstract: 80960SB
Contextual Info: Introduction to ¡960 Architecture 2 CH A PTER 2 IN TR O D U C T IO N TO i960™ A R C H ITE C TU R E This chapter provides an overview of the architecture on which the 80960 series o f processors is based. AN EMBEDDED 32-BIT ARCHITECTURE FROM INTEL The 80960SA/SB processor marks the continuation o f the i960 architecture series — an

diode byt 45

Abstract: 80960RP 80960JF AD10 MA11 272736
Contextual Info: A ADVANCE INFORMATION 80960RP THE IQ SERIES INTELLIGENT I/O MICROPROCESSOR • ■ ■ ■ ■ • Complies with PCI Local Bus Specification Revision 2.1 High Performance 80960JF Core ■ DMA Controller — Sustained One Instruction/Clock — Three Independent Channels

Embedded Applications Handbook 270646

Abstract: intel Multibus i handbook 230843 embedded controller handbook Mohawk 80960MC 80960 1989 intel I860 processor 270646 multibus II architecture specification
Contextual Info: 80960MC Hardware Designer’s Reference Manual June, 1989 Order Number: 271079-002 intei LITERATURE T o o rd er Intel Literature or obtain literature pricing inform ation in the U .S. and C anad a call or w rite Intel Literature Sales. In Europe and other international locations, please contact your local sales office or