80960M Search Results

80960MC

Contextual Info: Procedure Calls 4 CHAPTER 4 PROCEDURE CALLS This chapter describes the 80960MC processor’s procedure call and stack mechanism. It also describes the user-supervisor protection model, which provides protection for privileged procedures such as operating-system procedures.

processor

Abstract: 80960MC M82965
Contextual Info: Processor Management and Initialization g CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION This chapter describes the facilities for initializing and managing the operation of the 80960MC processor. Included is an overview of the processor-management facilities and a

intel 27127

Contextual Info: 80960MX SPECIFICATION UPDATE Release Date: July, 1996 Order Number: 272868-001 The 80960MX may contain design defects or errors known as errata. Characterized errata that may cause the 80960MX’s behavior to deviate from published specifications are documented in

M82965

Contextual Info: 80960MC PRODUCT OVERVIEW This chapter provides an overview o f the architecture o f the 80960M C processor. The 80960M C processor is the m ilitary-grade m em ber o f a new fam ily o f processors from Intel. This processor family is based on a new 32-bit architecture called the 80960 architecture. The

230843

Abstract: intel intellec prompt 48 210997 80960 Programmer Reference manual 210918 mohawk 80960MC A-20
Contextual Info: 80960MC Programmer’s Reference Manual 1988 Order Number: 271081-001 inter LITERATURE To order Intel literature write or call: Intel Literature Sales Toll Free Number: P.O. Box 58130 800 548-4725* Santa Clara, CA 95052-8130 Use the order blank on the facing page or call our Toll Free Number listed above to order literature.

80960MC

Contextual Info: Debugging 16 CHAPTER 16 DEBUGGING This chapter describes the tracing facilities of the 80960MC processor, which allow the monitoring of instruction execution. OVERVIEW OF THE TRACE-CONTROL FACILITIES The 80960MC processor provides facilities for monitoring the activity o f the processor by

A4490

Abstract: 80960MC LAD26 80960KA 80960KB i960 mc errata
Contextual Info: in te i 1.0 THE i960 MC PROCESSOR The 80960MC, a m em ber of Intel’s ¡960® 32-bit processor family, is ideally suited for embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960M C has a large register set, multiple parallel execution units

Contextual Info: ÄEW M i DNHF@IRßM!rilON in y 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at

80960MX

Abstract: 272868 intel DOC UPPER20 I960 mx 271194
Contextual Info: 80960MX SPECIFICATION UPDATE Release Date: July, 1997 Order Number: 272868-002 The 80960MX may contain design defects or errors known as errata which may cause the 80960MX to deviate from published specifications. Current characterized errata are documented in this Specification Update.

80960MC

Abstract: INTEL 80960 pipeline architecture M82965 80960
Contextual Info: Introduction to the 80960 Architecture 2 CHAPTER 2 INTRODUCTION TO THE 80960 ARCHITECTURE This chapter provides an overview of the architecture on which the 80960MC processor is based. A NEW 32-BIT ARCHITECTURE FROM INTEL The 80960MC processor is the military-grade member of a new family of processors from

80960MC

Abstract: M8259A
Contextual Info: Interrupts 10 CHAPTER 10 INTERRUPTS This chapter describes the 80960MC processor’s interrupt handling facilities. It also describes how interrupts are signaled. OVERVIEW OF THE INTERRUPT FACILITIES An interrupt is a temporary break in the control stream of a process so that the processor can

271060

Contextual Info: Ä ß M Ä K K S B D M F @ B IM T rD 0 W in te l 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 20 MHz — 9.4 MIPS* Sustained Execution at

Contextual Info: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military On-Chip Memory Management Unit — 4 Gigabyte Virtual Address Space per Task — 4 Kbyte Pages with Supervisor/User Protection High-Performance Embedded

a4490

Abstract: 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
Contextual Info: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

MQ80960MC

Abstract: LADT4 MQ80960MC-25/B MG80960MC 80960MC MQ80960MC-20/B DIODE 255 KO Intel 80960kb programmers reference LA01 80960KA
Contextual Info: in te i 80960M C EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT M ilita ry High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz On-Chip Floating-Point Unit

80960MC

Abstract: branch conditional unconditional instruction
Contextual Info: Instruction-Set Summary Q CHAPTER 6 INSTRUCTION-SET SUMMARY This chapter provides an overview of the instruction set for the 80960MC processor. Included is a discussion of the instruction format and a summary of the instruction groups and the instructions in each group.

80960MC

Contextual Info: Data Types and Addressing Modes 5 CHAPTER 5 DATA TYPES AND ADDRESSING MODES This chapter describes the data types that the 80960MC processor recognizes and the address­ ing modes that are available for accessing memory locations. DATA TYPES The processor defines and operates on the following data types:

80960MC

Abstract: AD30 M82965 FFFC0000
Contextual Info: Initialization CHAPTER 14 INITIALIZATION This chapter describes the hardware requirements for initializing the 80960MC processor and the BXU in a fault-tolerant system design. The basic minimum initialization requirements are described, as well as some of the available options. The exact initialization procedure depends on the type of

Embedded Applications Handbook 270646

Abstract: intel Multibus i handbook 230843 embedded controller handbook Mohawk 80960MC 80960 1989 intel I860 processor 270646 multibus II architecture specification
Contextual Info: 80960MC Hardware Designer’s Reference Manual June, 1989 Order Number: 271079-002 intei LITERATURE T o o rd er Intel Literature or obtain literature pricing inform ation in the U .S. and C anad a call or w rite Intel Literature Sales. In Europe and other international locations, please contact your local sales office or

80960MC

Abstract: XX10 XX20 XX40
Contextual Info: Fault Handling 12 CHAPTER 12 FAULT HANDLING This chapter describes the fault handling facilities of the 80960MC processor. The subjects covered include the fault-handling data structures, the required software support required for fault handling, and the fault handling mechanism. A reference section that contains detailed

M82786

Abstract: 82786 Intel 82786 82586 intel m8255 80960MC M8274 M8254 AP-59 82c502
Contextual Info: I/O Interface 5 CHAPTER 5 I/O INTERFACE The 80960M C processor supports 8, 16, 32-bit I/O devices by mapping them into its 4 G-byte memory address space. This chapter describes the design considerations for the interface between the 80960M C processor and I/O components. Severed exam ples illustrate the design concepts.

Contextual Info: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture ■ — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■

Contextual Info: O M lF < § » Ä T D [ i i] in te i 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at

a4490

Abstract: 80960MC Intel i960 architecture 80960KA 80960KB M8259A 273123
Contextual Info: 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit