MQ80960MC Search Results

D15105

Abstract: 44fl5 271060 754for
Contextual Info: in te i 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS1 Sustained Execution at 25 MHz On-Chip Memory Management Unit

Contextual Info: ÄEW M i DNHF@IRßM!rilON in y 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at

MG80960MC25

Abstract: MG80960MC20 MQ80960MC25 80960MC-20 5962-9094603MYX qml-38535 mg80960mc-25 MQ80960MC-25 MQ80960XA-20 5962-9094603MXX
Contextual Info: NOTICE OF REVISION NOR THIS REVISION DESCRIBED BELOW HAS BEEN AUTHORIZED FOR THE DOCUMENT LISTED. 1. DATE (YYMMDD) 96-06-18 Public reporting burden for this collection is estimated to average 2 hours per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the

271060

Contextual Info: Ä ß M Ä K K S B D M F @ B IM T rD 0 W in te l 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 20 MHz — 9.4 MIPS* Sustained Execution at

Contextual Info: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military On-Chip Memory Management Unit — 4 Gigabyte Virtual Address Space per Task — 4 Kbyte Pages with Supervisor/User Protection High-Performance Embedded

MQ80960MC

Abstract: LADT4 MQ80960MC-25/B MG80960MC 80960MC MQ80960MC-20/B DIODE 255 KO Intel 80960kb programmers reference LA01 80960KA
Contextual Info: in te i 80960M C EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT M ilita ry High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz On-Chip Floating-Point Unit

Contextual Info: O M lF < § » Ä T D [ i i] in te i 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at