PROCESSOR Search Results

Toshiba TB 1230 N

Abstract: TMPZ84C011 TMPZ84C011A TMP284C011 FO34
Contextual Info: TOSHIBA TMPZ84C011A 3. OPERATIONAL DESCRIPTIONS 3.1 ENTIRE BLOCK DIAGRAM AND OPERATION OF EACH BLOCK 3.1.1 Entire Block Diagram 110489 Figure 3.1.1 Entire Block Diagram MPUZ80-302 TOSHIBA TMPZ84C011A 3.1.2 Operation of Each Block The TMPZ84C011A largely consists of a processor MPU , a counter/timer circuit

TL500

Abstract: TL500CJ tl502 L501C
Contextual Info: TL500I, TL500C, TL501I, TL501C, TL502C, TL503C ANALOG-TO-DIGITAL-CONVERTER BUILDING BLOCKS D2477 DECEMBER 1979-REVISED JANUARY 1989 TL500I, TL500C, TL501I, TL501C ANALOG PROCESSORS • True Differential Inputs • Automatic Zero • Automatic Polarity •

18n8

Contextual Info: T IB P A D 18N8-6C HIGH-PERFORMANCE PROGRAMMABLE AD D RESS DECODER/NAND ARRAY D 3 0 8 6 , DECEMBER 1 9 8 7 Very High Speed Address Decoder Ideal for Use w ith High Speed Processors I/O Propagation Delay: 6 ns Max • Suitable for High Speed N A ND-NAND Logic

TMS320P17

Abstract: d6151 filter lark eng 1D2T ltw 8 pin TMS320P14 TMS320LC15
Contextual Info: TMS320C1X DIGITAL SIGNAL PROCESSORS J A N U A H Y 1 9 8 7 — R E V IS E D J U L Y 1991 • Performance Up to 8.77 MIPs Commercial and Military Versions Available • All TMS320C1x Devices are Object Code Compatible Operating Free-Air Temperature . . . 0°C to 70°C

ieee754

Abstract: TRW LSI Products IEEE-754 ABMT C3202
Contextual Info: Floating-Point Arithmetic T iT w V Fixed-point digital signal processor design requires careful attention to dynam ic range, limit cycles, and overflow conditions. Block floating-point is often used to extend the dynam ic range, but it carries with it significant bookkeeping overhead.

SN54382

Abstract: SN74F382
Contextual Info: SN54382, SN74F3B2 ARITHMETIC LOGIC/FUNCTION GENERATORS □ 2 9 3 2 , M A R C H 1 9 8 7 -R E V IS E D JA N U A R Y 1989 SN 54F382 . . J PACKAGE SN 74F382 . . DW OR N PACKAG E Ideally Suited for Hlgh-Density Economical Processors ITO P VIEW : 1 B1 C 2 AOC 3

RAV 14202

Abstract: TMS320C26
Contextual Info: SMJ320C26 DIGITAL SIGNAL PROCESSOR 68-P IN GB PIN G R ID A R R A Y C E R A M IC P A C K A G E t TO P V IE W 100-ns Instruction Cycle Time 1568 Words of Configurable On-Chip Data/Program RAM 1 2 3 4 5 6 7 6 9 10 11 256 Words of On-Chip Program ROM 128k Words of Data/Program Space

tic 2250

Abstract: 74AS887 1/triac tic 2250 S-8871 74AS887-1 rJ17
Contextual Info: 1 SN54AS887, SN74AS887 8 BIT PROCESSORS i • STL-AS Technology • Parallel 8 -Bit ALU w ith Expansion Inputs and Outputs • 13 Arithm etic and Logic Functions • 8 • 4 Instructions th at Manipulate Bits • Add and Subtract Immediate Instructions •

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

TMPR4951F

Contextual Info: TO SHIBA TMPR4951F TOSHIBA RISC PROCESSOR TENTATIVE TMPR4951F 64-bit RISC PROCESSOR 1. GENERAL DESCRIPTION The TMPR4951F is a 64-bit RISC (Reduced Instruction Set Computer) processor that is a lowcost, low-power processor developed for interactive consumer applications including LBP,

tyal 206

Abstract: TYAL
Contextual Info: TOSHIBA TMPR3907F TENTATIVE TOSHIBA RISC PROCESSOR TMPR3907F 32-Bit TX System RISC 1. GENERAL DESCRIPTION The TMPR3907F TX3907 is a TX39 family processor incorporating a 32-bit TX39/H core developed by Toshiba. Designed for use in OA equipment, the TX3907 also incorporates such peripheral circuits as a memory controller, a PCI

multibus ARCHITECTURE

Abstract: mcbsp tms 6000
Contextual Info: TMS320VC5416 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS095B – MARCH 1999 – REVISED OCTOBER 1999 D D D D D D D D D D D D D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU

mip 291

Abstract: mip 290
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025 – AUGUST 1998 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP)

Contextual Info: TPS3705-30, TPS3705-33, TPS3705-50 TPS3707-25, TPS3707-30, TPS3707-33, TPS3707-50 PROCESSOR SUPERVISORY CIRCUITS WITH POWER-FAIL SLVS184B – NOVEMBER 1998 – REVISED JANUARY 1999 TPS3705 . . . D PACKAGE TOP VIEW features D Power-On Reset Generator with Fixed

TXC07900AIBG

Abstract: TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117
Contextual Info: OED155 Device Dual STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07900 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED155, is a dual STM-1 SDH framer and overhead terminator, virtual tributary

S-PQFP-G144 footprint

Contextual Info: TMS320VC5410A Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS139 November 2000 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to

VTXP-6

Abstract: TXC-06951 g803 Motorola 0X69 TXC-06951-MB 98822
Contextual Info: VTXP-6 Device STM-1/STS-3 SDH/SONET TU/VT Processor and Cross Connect TXC-06951 DATA SHEET PRELIMINARY TXC-06951-MB, Ed. 5 March 2006 FEATURES APPLICATIONS • Supports two line ports using the standard byte wide 19.44 MHz Telecom Bus, or a single line port using the standard byte wide 77.76 MHz Telecom Bus.

Y446

Abstract: Y443 y441 POP-12 B1 Y447 Y442
Contextual Info: POP-12 Device OC-12 SONET/SDH Path Overhead Processor, Retimer, and Cross Connect TXC-06603 DATA SHEET PRODUCT PREVIEW DESCRIPTION • Path overhead POH processing for up to 12 x STS-1 SPEs or 4 x VC-4/STS-3c SPEs • 4 Tx and 4 Rx Pointer Tracking State Machines

CHIP EPROM AE12

Abstract: spru402 ST2328
Contextual Info: TMS320C6201 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS051G – JANUARY 1997 – REVISED NOVEMBER 2000 D High-Performance Fixed-Point Digital D D D D D D Signal Processor DSP TMS320C6201 – 5-ns Instruction Cycle Time – 200-MHz Clock Rate – Eight 32-Bit Instructions/Cycle

Contextual Info: TWL1103 VOICE-BAND AUDIO PROCESSOR VBAP SLWS108 – JULY 2000 D D D D D D 2.7-V Operation Two Differential Microphone Inputs, One Differential Earphone Output, and One Single-Ended Earphone Output Programmable Gain Amplifiers for Transmit, Receive, Sidetone, and Volume

SPRU132B

Contextual Info: SMQ320C32 DIGITAL SIGNAL PROCESSOR SGUS027B – APRIL 1998 – REVISED MARCH 1999 D D D D D D D D D D D Military Operating Temperature Range – 55°C to 125°C; QML Processing High-Performance Floating-Point Digital Signal Processor DSP SMQ320C32-50 (5 V)

TWL1102

Contextual Info: TWL1102 VOICE-BAND AUDIO PROCESSOR VBAP SLVS264 – NOVEMBER 1999 D 2.7-V Operation D Two Differential Microphone Inputs, One D D D D Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-Law or A-Law) Data D Available in a 32-Terminal TQFP Package

Contextual Info: TMS320VC5416 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS095E – MARCH 1999 – REVISED MAY 2000 D D D D D D D D D D D D D Separate 16-Bit Data Memory Buses and One Program Memory Bus 40-Bit Arithmetic Logic Unit ALU Including a 40-Bit Barrel Shifter and Two

C6701

Contextual Info: TMS320C6701 FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR SPRS067E – MAY 1998 – REVISED MAY 2000 D Highest Performance Floating-Point Digital D D D D D Signal Processor DSP TMS320C6701 – 8.3-, 6.7-, 6-ns Instruction Cycle Time – 120-, 150-, 167-MHz Clock Rate