HCT11 Search Results
HCT11 Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| CD54HCT112F3A | Texas Instruments | High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger 16-CDIP -55 to 125 |
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| CD74HCT112E | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
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| CD74HCT11E | Texas Instruments | High Speed CMOS Logic Triple 3-Input AND Gates 14-PDIP -55 to 125 |
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| CD74HCT11M96E4 | Texas Instruments | High Speed CMOS Logic Triple 3-Input AND Gates 14-SOIC -55 to 125 |
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| CD74HCT11M96 | Texas Instruments | High Speed CMOS Logic Triple 3-Input AND Gates 14-SOIC -55 to 125 |
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HCT11 Datasheets (2)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| HCT-1-152-15 | Coilcraft | Inductor: Power: 1.875u: -10% to 20%: 100K: Toroid | Original | 72.57KB | 1 | ||
| HCT-1-152-15L | Coilcraft | Power inductor, toroid, 20% tol, RoHS | Original | 78.93KB | 1 |
HCT11 Price and Stock
Nexperia 74HCT112PW,118Flip Flop, 74HCT112, JK, 19 ns, 70 MHz, 4 mA, 16 Pins, TSSOP - Tape and Reel (Alt: 74HCT112PW,118) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HCT112PW,118 | Tape & Reel | 24 Weeks | 5,000 |
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74HCT112PW,118 | 1,917 |
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74HCT112PW,118 | 959 |
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74HCT112PW,118 | 26 Weeks | 2,500 |
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74HCT112PW,118 | 4,708 |
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Get Quote | |||||||
Nexperia 74HCT11PW,118AND Gate, Triple, 3 Input, 14 Pins, TSSOP, 74HCT11 - Tape and Reel (Alt: 74HCT11PW,118) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HCT11PW,118 | Tape & Reel | 20 Weeks | 7,500 |
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74HCT11PW,118 | 5,706 |
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74HCT11PW,118 | Cut Tape | 1,040 | 1 |
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| 74HCT11PW,118 | Tape & Reel | 1,040 | 100 |
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74HCT11PW,118 | 1,440 | 1 |
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74HCT11PW,118 | 1 |
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74HCT11PW,118 | 2,853 |
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Get Quote | |||||||
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74HCT11PW,118 | 20 Weeks | 7,500 |
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74HCT11PW,118 | 22 Weeks | 2,500 |
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Get Quote | ||||||
Nexperia 74HCT11D-Q100JAND Gate, Triple, 3 Input, 14 Pins, SOIC, 74HCT11 - Tape and Reel (Alt: 74HCT11D-Q100J) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HCT11D-Q100J | Tape & Reel | 22 Weeks | 5,000 |
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74HCT11D-Q100J | 2,705 |
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74HCT11D-Q100J | 2,230 | 1 |
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74HCT11D-Q100J | 22 Weeks | 5,000 |
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74HCT11D-Q100J | 24 Weeks | 2,500 |
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Get Quote | ||||||
Nexperia 74HCT11DB,118AND Gate, Triple, 3 Input, 14 Pins, SSOP, 74HCT11 - Tape and Reel (Alt: 74HCT11DB,118) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HCT11DB,118 | Tape & Reel | 2,000 |
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Get Quote | ||||||
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74HCT11DB,118 | 1,888 | 1 |
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Buy Now | ||||||
Nexperia 74HCT112D-Q100J74HCT112D-Q100/SOT109/SO16/12 NC : 935691595118 - Tape and Reel (Alt: 74HCT112D-Q100J) |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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74HCT112D-Q100J | Tape & Reel | 20 Weeks | 5,000 |
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Buy Now | |||||
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74HCT112D-Q100J |
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74HCT112D-Q100J | 9,572 |
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Get Quote | |||||||
HCT11 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
IC 74HC112
Abstract: 74HC112
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Original |
cd54/74hc112cd54/74hct112schs141ahc112+8 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141F Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
CD54
Abstract: CD54HC11 CD54HC11F3A CD54HCT11 CD54HCT11F3A CD74HC11 CD74HCT11 HC11
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Original |
hct11cd54hc11cd74hc11cd54hct11+6 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+4 | |
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Contextual Info: 74HC/HCT11 T R IPLE 3-INPUT A N D GATE FEATURES T Y P IC A L • Output capability: standard • I q £ category: SSI SYMBOL G EN ERA L DESCRIPTION tp H iy tPLH propagation delay nA, nB, nC to n Y C| input capacitance CPD power dissipation capacitance per gate |
OCR Scan |
74hc/hct1174hct | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
hc112hct11cd54hc112cd74hc112+4 | |
CD54
Abstract: CD54HC11 CD54HC11F3A CD54HCT11 CD54HCT11F3A CD74HC11 CD74HCT11 HC11
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Original |
hct11cd54hc11cd74hc11cd54hct11+6 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description |
Original |
cd54hc11cd74hc11cd54hct11cd74hct11+2 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description |
Original |
cd54hc11cd74hc11cd54hct11cd74hct11+2 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
CD54HC112
Abstract: CD54HC112F3A CD54HCT112 CD54HCT112F3A CD74HC112 CD74HCT112
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Original |
hc112hct11cd54hc112cd74hc112+6 | |
IN74ACT112D
Abstract: IN74ACT112N
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Original |
in74act112ls/als112hc/hct112in74act112n+1 | |
IN74AC11D
Abstract: 5540a IN74AC11N
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Original |
in74ac11ls/als11hc/hct11in74ac11n+2 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273D High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised July 2003 Features Description |
Original |
cd54hc11cd74hc11cd54hct11cd74hct11+2 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
hc112hct11cd54hc112cd74hc112+4 | |
74HCT11
Abstract: 74hc11
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Original |
cd54/74hc11cd54/74hct11schs273ahct11+8 | |
CD74HC112
Abstract: 74HCT 74LS CD74HC112E CD74HCT112
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Original |
hc112hct11cd74hc112cd74hct112+4 | |
KK74AC112
Abstract: KK74AC112D KK74AC112N
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Original |
kk74ac112ls/als112hc/hct112kk74ac112n+2 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, HCT11, HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description |
Original |
hct11cd54hc11cd74hc11cd54hct11+2 | |
Scans-052Contextual Info: CD54HC112F3A, HCT112F3A June 1997 Dual J-K Flip-Flop with Set and Reset File Number 3774.1 Functional Diagram This device is fully compliant to the requirements of paragraph 1.2.1 of MIL-STD-883. The CD54HC/HCT112F3A utilizes silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL |
OCR Scan |
cd54hc112f3acd54hct112f3amil-std-883cd54hc/hct112f3a+6 | |
IN74AC112
Abstract: IN74AC112D IN74AC112N
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Original |
in74ac112ls/als112hc/hct112in74ac112n+1 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |