CD74HC11 Search Results
CD74HC11 Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| CD74HC112E | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 |
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| CD74HC112NSR | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SO -55 to 125 |
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| CD74HC11E | Texas Instruments | High Speed CMOS Logic Triple 3-Input AND Gates 14-PDIP -55 to 125 |
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| CD74HC11M96 | Texas Instruments | High Speed CMOS Logic Triple 3-Input AND Gates 14-SOIC -55 to 125 |
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| CD74HC112M96 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 |
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CD74HC11 Datasheets (107)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| CD74HC11 | Texas Instruments | High Speed CMOS Logic Triple 3-Input AND Gates | Original | 32.35KB | 6 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Original | 43.47KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112 | Texas Instruments | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Original | 54.05KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112E | Texas Instruments | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Original | 54.05KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112E | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | Original | 650.43KB | 18 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112E | Texas Instruments | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Original | 234.56KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112E | Texas Instruments | CD74HC112 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | Original | 774.28KB | 20 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112E | Harris Semiconductor | Dual J-K Flip-Flop with Set and Reset | Scan | 432.86KB | 5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112E | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112E96 | Texas Instruments | Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | Original | 41.05KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112EE4 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Original | 373.18KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112EE4 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | Original | 650.43KB | 18 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112EE4 | Texas Instruments | CD74HC112 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 | Original | 774.28KB | 20 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112H | Harris Semiconductor | Dual J-K Flip-Flop with Set and Reset | Scan | 432.86KB | 5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112M | Harris Semiconductor | Dual J-K Flip-Flop with Set and Reset | Scan | 432.86KB | 5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112M96 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 | Original | 650.43KB | 18 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112M96 | Texas Instruments | HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET | Original | 54.05KB | 8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112M96 | Texas Instruments | CD74HC112 - High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-SOIC -55 to 125 | Original | 774.28KB | 20 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112M96 | Unknown | Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. | Historical | 32.93KB | 1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CD74HC112M96E4 | Texas Instruments | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | Original | 373.18KB | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CD74HC11 Price and Stock
Texas Instruments CD74HC11EAND Gate 3-Element 3-IN 14-Pin PDIP Tube |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC11E | 7,299 | 448 |
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| CD74HC11E | 5,080 | 448 |
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| CD74HC11E | 1,635 | 448 |
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| CD74HC11E | 950 | 448 |
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| CD74HC11E | 912 | 5 |
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| CD74HC11E | 700 | 448 |
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CD74HC11E | 912 | 1 |
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CD74HC11E | 18 |
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CD74HC11E | 539 |
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| CD74HC11E | 14 |
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CD74HC11E | 16,671 | 1 |
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CD74HC11E | 766 | 1 |
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Texas Instruments CD74HC11MAND Gate 3-Element 3-IN CMOS 14-Pin SOIC Tube |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC11M | 4,400 | 416 |
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| CD74HC11M | 4,250 | 416 |
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| CD74HC11M | 4,000 | 416 |
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| CD74HC11M | 3,475 | 416 |
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| CD74HC11M | 1,000 | 416 |
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| CD74HC11M | 733 | 416 |
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CD74HC11M | 19,369 | 1 |
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Harris Semiconductor CD74HC11MCD74HC11M |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC11M | 2,000 | 416 |
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Buy Now | ||||||
| CD74HC11M | 665 | 416 |
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CD74HC11M | 3,665 | 1 |
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Harris Semiconductor CD74HC11ECD74HC11E |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC11E | 1,000 | 448 |
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CD74HC11E | 484 |
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CD74HC11E | 6,277 |
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| CD74HC11E | 20 |
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CD74HC11E | 1,000 | 1 |
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Texas Instruments CD74HC112PWRFlip Flop JK-Type Neg-Edge 2-Element 16-Pin TSSOP T/R |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CD74HC112PWR | Cut Strips | 57 | 12 Weeks | 1 |
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CD74HC112PWR | 274 | 1 |
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CD74HC112PWR | 219 |
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CD74HC112PWR | 2,000 |
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CD74HC11 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141F Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
CD54
Abstract: CD54HC11 CD54HC11F3A CD54HCT11 CD54HCT11F3A CD74HC11 CD74HCT11 HC11
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hct11cd54hc11cd74hc11cd54hct11+6 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
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cd54hc112cd74hc112cd54hct112cd74hct112+4 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
hc112hct11cd54hc112cd74hc112+4 | |
CD54
Abstract: CD54HC11 CD54HC11F3A CD54HCT11 CD54HCT11F3A CD74HC11 CD74HCT11 HC11
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hct11cd54hc11cd74hc11cd54hct11+6 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description |
Original |
cd54hc11cd74hc11cd54hct11cd74hct11+2 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description |
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cd54hc11cd74hc11cd54hct11cd74hct11+2 | |
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Contextual Info: CD54HCT11, CD74HC11, CD74HCT11 S E M I C O N D U C T O R High Speed CMOS Logic Triple 3-Input AND Gate August 1997 Features Description • Buffered Inputs The Harris CD54HCT11, CD74HC11, and CD74HCT11 logic gates utilize silicon gate CMOS technology to achieve |
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cd54hct11cd74hc11cd74hct1174hct+1 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
CD54HC112
Abstract: CD54HC112F3A CD54HCT112 CD54HCT112F3A CD74HC112 CD74HCT112
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hc112hct11cd54hc112cd74hc112+6 | |
CD54HC11
Abstract: CD54HC11F3A CD54HCT11 CD54HCT11F3A CD74HC11 CD74HCT11 HC11 CD54
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hct11cd54hc11cd74hc11cd54hct11+6 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Data sheet acquired from Harris Semiconductor SCHS273D High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised July 2003 Features Description |
Original |
cd54hc11cd74hc11cd54hct11cd74hct11+2 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
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hc112hct11cd54hc112cd74hc112+4 | |
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Contextual Info: ASSESS? CD54HCT11, CD74HC11, CD74HCT11 High Speed CMOS Logic Triple 3-Input AND Gate August 1997 Features Description • Buffered Inputs The Harris C D54H CT11, CD74HC11, and C D74H CT11 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power |
OCR Scan |
cd54hct11cd74hc11cd74hct1174hct | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description |
Original |
hct11cd54hc11cd74hc11cd54hct11+2 | |
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Contextual Info: Texas CD54HCT11, CD74HC11, CD74HCT11 In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SCHS273 High Speed CMOS Logic Triple 3-Input AND Gate August 1997 Features Description • Buffered Inputs The Harris C D54H CT11, CD74HC11, and C D74H CT11 |
OCR Scan |
cd54hct11cd74hc11cd74hct1174hct | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
cd54hc112cd74hc112cd54hct112cd74hct112+3 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description |
Original |
cd54hc11cd74hc11cd54hct11cd74hct11+2 | |
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Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description |
Original |
cd54hc11cd74hc11cd54hct11cd74hct11+2 | |
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Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003 |
Original |
hc112hct11cd54hc112cd74hc112+4 | |
74ls gate symbols
Abstract: 74HCT 74LS CD54 CD54HCT11 CD74HC11 CD74HC11E CD74HCT11 HC11
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Original |
hct11cd54hct11cd74hc11cd74hct11+7 | |
CD54HC112
Abstract: CD54HC112F3A CD54HCT112 CD54HCT112F3A CD74HC112 CD74HCT112
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Original |
hc112hct11cd54hc112cd74hc112+6 | |