HCT112 Search Results

IN74ACT112D

Abstract: IN74ACT112N
Contextual Info: TECHNICAL DATA IN74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

KK74AC112

Abstract: KK74AC112D KK74AC112N
Contextual Info: TECHNICAL DATA KK74AC112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs.

Scans-052

Contextual Info: CD54HC112F3A, HCT112F3A June 1997 Dual J-K Flip-Flop with Set and Reset File Number 3774.1 Functional Diagram This device is fully compliant to the requirements of paragraph 1.2.1 of MIL-STD-883. The CD54HC/HCT112F3A utilizes silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL

IN74AC112

Abstract: IN74AC112D IN74AC112N
Contextual Info: TECHNICAL DATA IN74AC112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS

KK74ACT112

Abstract: KK74ACT112D KK74ACT112N
Contextual Info: TECHNICAL DATA KK74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The KK74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The KK74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

IN74ACT112N

Abstract: IN74ACT112D
Contextual Info: TECHNICAL DATA IN74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

54LS

Contextual Info: CD54HC112/3A HCT112/3A S E M I C O N D U C T O R Dual J-K Flip-Flop with Set and Reset June 1997 Description Functional Diagram This device is fully compliant to the requirements of paragraph 1.2.1 of MIL-STD-883. 1S 1J The CD54HC/HCT112/3A utilizes silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL

HCT112

Abstract: HCT-112 74HC 74HCT S0 1J
Contextual Info: 7 4H C /H C T 112 flip-flops DUAL JK FLIP-FLOP WITH SET AND RESET; IMEGATIVE-EDGE TRIGGER FEATURES TYPICAL The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky T T L LSTTL . They are specified in compliance w ith JEDEC standard no.7A.

HCT-112

Abstract: IN74ACT112N IN74ACT112D
Contextual Info: IN74ACT112 DUAL J-K FLIP-FLOP WITH SET AND RESET High-Speed Silicon-Gate CMOS • • • • The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS

IN74ACT112N

Abstract: IN74ACT112D
Contextual Info: TECHNICAL DATA IN74ACT112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74ACT112 is identical in pinout to the LS/ALS112, HC/HCT112. The IN74ACT112 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

IN74AC112N

Abstract: IN74AC112 IN74AC112D
Contextual Info: TECHNICAL DATA IN74AC112 Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC112 is identical in pinout to the LS/ALS112, HC/HCT112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS

MAX232

Contextual Info: 74HC/HCT112 flip-flops DUAL JK FLIP-FLOP WITH SET AND RESET; NEGATIVE-EDGE TRIGGER FEATURES • • • TYPICAL Asynchronous set and reset Output capability: standard l£ £ category: flip-flops GENERAL DESCRIPTION ic p 1K JT u IT HCT 17 15 18 19 15 19 tP H l/

IC06 74HC/HCT/HCU/HCMOS Logic Package Information

Abstract: 74HC112D 74HC112DB 74HC112N 74HC112PW 74HCT112D 74HCT112DB 74HCT112N w 20 nk 50 z supersedes data of december 1990
Contextual Info: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT112

IC 74HC112

Abstract: 74HC112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

NSP 233

Abstract: D15114
Contextual Info: 74HC/HC T112 flip-flops DUAL JK FLIP-FLOP W ITH SET AND RESET; NEGATIVE-EDGE TRIGGER FEATURES TYPICAL • Asynchronous set and reset • Output capability: standard • IQ0 category: flip-flops PARAMETER SYMBOL U NIT CONDITIONS HC HCT 17 15 18 19 15 19 ns

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

CD54HC112

Abstract: CD54HC112F3A CD54HCT112 CD54HCT112F3A CD74HC112 CD74HCT112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

HCT76

Abstract: T112 74HCT MM54HCT112 MM54HCT76 MM74HCT112 MM74HCT76 n-sb3
Contextual Info: MM54HCT76 MM74HCT76 HCT112 HCT112 Dual J-K Flip-Flops with Preset and Clear General Description These flip-flops utilize advanced silicon-gate CMOS technology They have input threshold and output drive similar to LS-TTL with the low standby power of CMOS

BPW22A

Abstract: cm .02m z5u 1kv pin configuration of BFW10 la4347 B2X84 TDA3653 equivalent TRIAC TAG 9322 HEF40106BP equivalent fx4054 core dsq8
Contextual Info: Contents Page Page New product index Combined index and status codes viii x Mullard approved components BS9000, CECC, and D3007 lists CV list Integrated circuits Section index xliii 1 5 Standard functions LOGIC FAMILIES CMOS HE4000B family specifications CMOS HE4000B family survey

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003

Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54HC112, CD74HC112, HCT112, HCT112 Data sheet acquired from Harris Semiconductor SCHS141H Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised October 2003