74HC11 Search Results

IC 74HC112

Abstract: 74HC112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000

74ls112 pin diagram

Abstract: 74HC112
Contextual Info: GD54/74HC112, GD54/74HCT112 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 54/74LS112. They consist of two J-K flip-flops with individual J, K, CLOCK, PRESET, and CLEAR in­ puts. These flip-flops are edge sensitive to the clock

74hc11

Contextual Info: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 5 — 16 December 2011 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74HC11A

Abstract: 74HC11
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC11 Triple 3-In p u t A N D Gate High-Performance Silicon-Gate CMOS The MC54/74HC11 is identical in pinout to the LS11, The device inputs are com ­ patible w ith standard CMOS outputs; w ith pullup resistors, they are com patible w ith

74hct11m

Abstract: 74hc11
Contextual Info: Technical Data CD54/74HC11 CD54/74HCT11 File N um ber 1475 High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: • B utte red inpu ts ■ Typical propagation delay = 8 ns @ VCc - 5 V, CL = 15 pF, 7« = 25° C T E R M IN A L A S S IG N M E N T The R C A-CD54/74HC11 and C D 54/74HCT11 lo gic gates

JK flip flop IC

Abstract: J-K Flip flops 4000B 74LS113 M74HC113 M74HC113P "J-K Flip flops"
Contextual Info: M IT S U B IS H I HIGH S P E E D C M O S sc< M 74HC113P s v x n.>A'C D U A L J -K F L IP -F L O P W IT H S E T DESCRIPTION The M 74H C 113 is a sem iconductor integrated circu it con­ PIN CONFIGURATION TOP VIEW sisting of tw o n e g a tiv e -e d g e trig g e re d J-K flip flops w ith in­

74HCT11

Abstract: 74hc11
Contextual Info: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54/74HC11, CD54/74HCT11 Data sheet acquired from Harris Semiconductor SCHS273A High Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs

74HC113

Abstract: MC74HCXXXN S-10
Contextual Info: MOTOROLA SE M IC O N D U C TO R TECHNICAL DATA MC54/74HC113 D u a l J -K F lip -F lo p w ith S e t High-Performance Silicon-Gate CM O S J SUFFIX CERAMIC CASE 632-08 T h e M C 5 4 / 7 4 H C 1 13 is id e n tic a l in p in o u t t o th e L S 1 1 3 . T h e d e v ic e in p u ts a re

74hc11

Contextual Info: \ - + Technical Data CD54/74HC11 CD54/74HCT11 HARRIS SEMICOND 3 -2- 1-00 File N um b er SECTOR 27E D H 4302271 1475 001747= 2 • H A S High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: ■ B uffe red inputs m Typical propagation delay = 8 ns r A = 25° c

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC113 Dual J-K Flip-Flop w ith Set H igh-Perform ance S ilico n -G ate C M O S The M C 5 4 /7 4 H C 1 13 is id entical in p in o u t to th e L S 1 13. T he device in p u ts are co m p a tib le w ith standard C M O S o u tp u ts ; w ith pullup resistors, th e y are c o m p a tib le

74HC112 pin diagram

Abstract: 74HC112 74HC112D IC 74HC112
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC112 D u al J-K Flip-Flop w ith S e t and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS T h e M C 5 4 / 7 4 H C 1 1 2 is id e n ti c a l in p i n o u t : o t h e L S 1 12. T h e d e v ic e in p u t s are

MC54HC112

Contextual Info: MOTOROLA • SEMICONDUCTOR TECHNICAL DATA MC54/74HC112 Dual J-K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620-09 High-Performance Silicon-Gate CMOS The M C 54/74H C 11 2 is id entical in p in o u t to the LS112. The device in p u ts are c o m p a tib le w ith standard C M O S o u tp u ts ; w ith p u llu p resistors, th e y are c o m p a tib le

74hc11

Contextual Info: 74HC11-Q100; 74HCT11-Q100 Triple 3-input AND gate Rev. 2 — 22 March 2013 Product data sheet 1. General description The 74HC11-Q100; 74HCT11-Q100 is a triple 3-input AND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in

74ls112 pin diagram

Contextual Info: TOSHIBA LOG IC/MEMOR Y IME 0 I ^0 1 724 0 0 0 1 0 0 3 0 o| — 74HC112P/F TC 74HC112P/F DUAL J-K FLIP FLOP WITH PRESET AND CLEAR The 74HC112 is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2M0S technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining

74HC112

Abstract: data sheet IC 74HC112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HC112NSR
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141B Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised March 2002

74hc113

Abstract: 74HCT113 GD74HCT11 74HC GD54HC113 GD74HC113 74LS113
Contextual Info: GD54/74HC113, GD54/74HCT113 DUAL J-K FLIP-FLOPS WITH PRESET General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 13. They consist of two J-K flip-flops with individual J, K, Clock, and Preset inputs. These flip-flops are edge sensitive to the clock input and

74HC112

Contextual Info: • MOTOROLA SEMICONDUCTOR M TECHNICAL DATA IH0T4 blE D b3b75se OCHITHO 3b4 otorola se clogic MC54/74HC112 Dual J -K Flip-Flop w ith Set and Reset J SUFFIX CERAMIC CASE 620*09 High-Performance Silicon-Gate CMOS T he M C 54/74H C 11 2 is id en tic a l in p in o u t to th e L S 112. T he device in p u ts are

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC54/74HC113 Dual J-K Flip-Flop w ith Set High-Performance Silicon-Gate CM OS J SUFFIX CERAMIC CASE 632-08 T h e M C 5 4 /7 4 H C 1 1 3 is id e n tic a l in p in o u t to th e L S 113. T h e d e v ic e in p u ts a re [f 1 II u u

LM 4017 decade counter driver

Abstract: 74HC7244A 74HCT7007A 74HC11A 74HC85A 74HC147 decimal to binary encoder cmos 4008 74HC21A 74HC07A 74HC7244
Contextual Info: 2.H IG H SPEED CMOS SELECTION GUIDE NÄ N D NOR A ND OR IN V E R T E R ,B U F FE R 74HC00A 74HCT00A 74HC03A 74HC10A 74HC20A 74HC30 71HC132A 74HC133A GATE 74HC02A 74HCT02A 74HC27A 74HC4002A 74HC4078 74HC08A 74HCT08A 74HC09A 74HC11A 74HC21A 74HC32A 74HCT32A 74HC4072

Contextual Info: Technical Data CD54/74HC11 CD54/74HCT11 File N um ber 1475 High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: • B u ffe re d inputs ■ Typical propagation delay - 8 ns < ' Vcc = 5 V , C L = 15 pF, 7a = 25° C T E R M IN A L A S S IG N M E N T

74HC114

Contextual Info: SN 54HC114, SN 74HC114 DUAL J K NEGATIVE EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR. AND COMMON CLOCK D2684, DECEMBER 1982-REVISED SEPTEMBER 1987 c lr C C2 l j[ 3 ip r e C 4 iq C 5 iq C 6 gndC ik Dependable Texas Instrum ents Quality and Reliability

HCT114

Abstract: 74HC11 datasheet 74hc11 74HC11D 74HC11DB 74HC11N 74HCT11 74HCT11D 74HCT11DB 74HCT11N
Contextual Info: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 04 — 25 March 2010 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74HC11

Abstract: 74HCT11 74HC11D 74HC11N 74HCT11D 74HCT11DB 74HCT11N 74HC11DB 74HCT11N pin diagram 74HCT11P
Contextual Info: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 03 — 9 February 2010 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .

74hc11

Abstract: 74HC11A
Contextual Info: MOTOROLA H SE M IC O N D U C T O R TECHNICAL DATA MC54/74HC11 Triple 3-Input A N D Gate High-Performance Silicon-Gate C M O S J SU F F IX C E R A M IC C A S E 632-08 The MC54/74HC11 is identical in pinout to the LS11. The device inputs are com­ patible with standard C M O S outputs; with pullup resistors, they are compatible with