DQ0DQ15 Search Results

tr8c

Abstract: TMS28F200
Contextual Info: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture

NCC equivalent

Contextual Info: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors

Contextual Info: SMJ416160, SMJ418160 1048576-WORD BY 16-BIT HIGH-SPEED DRAM 1 SGMS720A - APRIL 1995 - REVISED JUNE 1995 XXX PACKAGE TOP VIEW ACCESS ACCESS ACCESS TIME TIME TIME '41x160-60 41x160-70 '41x160-80 • • • • • • • • tRAC MAX 60 ns 70 ns SO n* *CAC

E3235

Contextual Info: TOSHIBA TENTATIVE TC59WM815/07/03BFT-70,-75,-80 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDSX4BANKSX16-BITS SYNCHRONOUS DYNAMIC RAM 8,388,608-WORDSX4BANKSX8-BITS SYNCHRONOUS DYNAMIC RAM 16,777,216-WORDSX4BANKSX4-BITS SYNCHRONOUS DYNAMIC RAM

Video RAM

Abstract: TMS55165
Contextual Info: TMS55165 262144 BY 16-BIT MULTIPORT VIDEO RAM SMVS165B-AUGUST1992-flEVISED JANUARY 1993 DGH PACKAGEt TOP VIEW DRAM : 262 144 Words x 16 Bits SAM: 256 Words x 16 Bits Dual Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and SAM Ports

Contextual Info: TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY S M K S 891C - A U G U S T 1996 - R EVISED O C TO BE R 1997 This data sheet is applicable to TMS418160As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section.

IS42VS16100E

Abstract: 42VS16100E IS42VS16100E-75BLI
Contextual Info: IS42VS16100E 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 133, 100, 83 MHz • Fully synchronous; all signals referenced to a positive clock edge • Two banks can be operated simultaneously and independently • Dual internal bank controlled by A11

Contextual Info: TMS55160 262144 BY 16-BIT MULTIPORT VIDEO RAM SMVS160B-AUGUST1992-REVISED JANUARY 1993 * * * * * DGH PACKAGEt DRAM : 262144 Words x 16 Bits SAM: 256 Words x 16 Bits TOP VIEW Dual Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and

Contextual Info: TMS416160, TMS416160P 1 048 576-WORD BY 16-BIT HIGH-SPEED DYNAMIC RANDOM-ACCESS MEMORIES SMKS660-DECEMBER 1992 Organization. . . 1 048 576 x 16 RE P A C K A G E t DC P A C K AG E t TOP VIEW (TOP VIEW) Single 5-V Supply (10% Tolerance) '416160/P-60 '416160/P-70

Contextual Info: Very Low Power CMOS SRAM 128K X 16 bit BS616LV2016 Pb-Free and Green package materials are compliant to RoHS n FEATURES n DESCRIPTION Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V Ÿ Very low power consumption : VCC = 3.0V Operation current : 30mA Max. at 55ns

IS42S16160D

Abstract: IS42S16160D-7TLI
Contextual Info: IS42S83200D, IS42S16160D IS45S83200D, IS45S16160D 32Meg x 8, 16Meg x16 JUNE 2009 256-MBIT SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed

SAMSUNG MCP

Abstract: ECH information KBB0xB400M BA102 ba4901 UtRAM Density BA5101 samsung NAND memory BGA180 ba30 transistor
Contextual Info: Preliminary MCP MEMORY KBB0xB400M Document Title Multi-Chip Package MEMORY 64M Bit 8M x8/4M x16 Dual Bank NOR Flash *2 / 256M Bit (16Mx16) NAND Flash / 64M Bit (4Mx16) UtRAM Revision History Revision No. History 0.0 Initial Draft (64M NOR Flash M-die_rev1.1)

NT5DS8M16FS-5T

Abstract: NT5DS8M16FS-6K NT5DS8
Contextual Info: NT5DS8M16FT NT5DS8M16FS 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2 & 2.5 for 6K, 2, 2.5, & 3 for 5T

Nanya nt5ds8m16fs

Abstract: NT5DS8M16FS NT5DS8M16FT-5TI NT5DS8M16FS-5T DDR333 DDR400 NT5DS8M16 NT5DS8M16FT-6KI NT5DS8M16FT
Contextual Info: NT5DS8M16FT-5TI NT5DS8M16FS-5TI NT5DS8M16FT-6KI NT5DS8M16FS-6KI 128Mb DDR SDRAM Features • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8

NT5DS16M16BF-6K

Abstract: NT5DS32M8BT NT5DS16M16BT-6K NT5DS16M16BT NT5DS64M4BT NT5DS32M
Contextual Info: NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG 256Mb DDR SDRAM Features • Data mask DM for write data • DLL aligns DQ and DQS transitions with CK transitions

NT5SV8M16FS

Abstract: Nanya NT5SV8M16FS NT5SV8M16FS-75BI Nanya NT5SV8M16FS-75Bi NT5SV8M16FS-6KI NT5SV8M16FT NT5SV8M16FT-6KI nt5sv8m16fs-6k 54-PIN NT5SV8M16FT-6K
Contextual Info: NT5SV8M16FT-6KI NT5SV8M16FS-6KI NT5SV8M16FT-75BI NT5SV8M16FS-75BI 128Mb Synchronous DRAM • • • • • • • • • • • • Features • High Performance: Maximum Operating Speed CAS Latency PC166 6KI PC133 (75BI) 2 7.5 10 ns 3 6 7.5 ns •

TE28F640J3C-120

Abstract: TE28F128J3C-120 INTEL 28F320J3 28F128J3 28F256K18 TE28F320J3C110 28F320J3 RC28F640J3C-120 28F640J3 28F640J3 reliability
Contextual Info: 3 Volt Intel StrataFlash Memory 28F128J3, 28F640J3, 28F320J3 x8/x16 Datasheet Product Features • ■ ■ Performance — 110/115/120/150 ns Initial Access Speed — 25 ns Asynchronous Page-Mode Reads — 32-Byte Write Buffer —6.8 µs per Byte Effective

Contextual Info: V58C2128 804/404/164 SB HIGH PERFORMANCE 128 Mbit DDR SDRAM 4 BANKS X 4Mbit X 8 (804) 4 BANKS X 2Mbit X 16 (164) 4 BANKS X 8Mbit X 4 (404) 5 6 DDR400 DDR333 7.5 ns 7.5 ns Clock Cycle Time (tCK2.5) 6ns 6 ns Clock Cycle Time (tCK3) 5ns 6 ns 200 MHz 166 MHz Clock Cycle Time (tCK2)

IS42S81600B

Abstract: 42S16800B IS42S16800B-7TLI 2MX16X4 IS42S16800B IS42S16800B-6TL
Contextual Info: IS42S81600B IS42S16800B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM JUNE 2009 FEATURES • Clock frequency: 167, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed

Contextual Info: S98WS256PD0-003 Stacked Multi-chip Product MCP 256 Mbit (16 M x 16-Bit) 1.8 V Burst Mode Flash Memory 128 Mb (8M x 16-Bit) 1.8 V CellularRAM Type 2, Burst Mode Data Sheet S98WS256PD0-003 Cover Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion

Contextual Info: W28J320B/T 32M 2M x 16/4M × 8 BOOT BLOCK FLASH MEMORY Table of Contents1. GENERAL DESCRIPTION. 3 2. FEATURES . 3

NT5SV16M4DT

Abstract: NT5SV4M16DT
Contextual Info: NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT 64Mb Synchronous DRAM Features • High Performance: -6K -7K -7 Units fCK Clock Frequency 166 133 143 133 143 MHz tCK Clock Cycle 6 7.5 7 7.5 7 ns CL=2 CL=3 CKs CL CAS Latency tAC Clock Access Time1 CL=3 CL=2 CL=3 - —

S98WS512

Contextual Info: S98WS512PE0FW005 Stacked Multi-chip Product MCP 512 Mbit (32M x 16-Bit) Stacked Burst Mode, Simultaneous Read/Write Flash Memory with 256 Mbit (16M x 16-bit) Mobile SDRAM on Shared Bus S98WS512PE0FW005 Cover Sheet Data Sheet (Advance Information) Notice to Readers: This document states the current technical specifications regarding the Spansion

Contextual Info: K8D6x16UTM / K8D6x16UBM FLASH MEMORY Document Title 64M Bit 8M x8/4M x16 Dual Bank NOR Flash Memory Revision History Revision No. History Draft Date Remark 0.0 Initial Draft January 10, 2002 Preliminary 1.0 Final Specification May 22, 2002 Final 1.1 Revised