DQ08 Search Results

HFBR-X41XT

Abstract: Marking code 44t HEDS-9200 marking 44t HFBR-X41X
Contextual Info: HEWLETT-PACKARD/ CMPNTS blE T> • 4447S6M DQ08762 W hpl HEWLETT ■¿VU PACKARD 5 MBd Low Cost Fiber Optic Receiver Technical Data HFBR-24X2 Series Description The HFBR-24X2 fiber optic receiver is designed to operate with the Hewlett-Packard HFBR-14XX fiber optic

AS8S512K3

Contextual Info: ADVANCED iPEM 64 Mb ASYNC SRAM AS8S2M32PEC 64Mb, 2Mx32 CMOS 3.3V, High Speed Static RAM Integrated Plastic Encapsulated Microcircuit FEATURES DESCRIPTION Integrated Real-Time Memory Array Solution No latency or refresh cycles Parallel Read/Write Interface

Memory

Abstract: FTS8L32512V
Contextual Info: FTS8L32512V 512Kx32 SRAM Module.3.3V FEATURES DESCRIPTION DSP Memory Solution The FTS8L32512V is a high speed, 3.3V, 16 megabit SRAM. The device is available with access times of 12, 15, 17 and 20ns allowing the creation of a no wait state DSP and RISC microprocessor memory solutions.

Contextual Info: IBM041841RLAA IBM043641RLAA Preliminary 128K X 36 & 256K X 18 SRAM Features • 128K x 36 or 256K x 18 Organizations • Registered Outputs • CMOS Technolgy • Asynchronous Output Enable and Power Down Inputs • Synchronous Pipeline Mode Of Operation with

Contextual Info: •HYUNDAI H Y 6 7 V 1 8 1 0 0 /1 0 1 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and pipelined output. All synchronous inputs pass through registers controlled by a positiveedge triggered clock K .

Contextual Info: WEDPY256K72V-XBX 256Kx72 Synchronous Pipeline SRAM FEATURES DESCRIPTION  Fast clock speed: 100, 133, 150, 166 and 200* MHz The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate two 256K x 36 SRAMs

Contextual Info: Mobile 3rd Generation Intel Core Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Datasheet, Volume 1 of 2 June 2013 Document Number: 326768-006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

Contextual Info: EDI8F32123C ^ E D I ELECTRONIC DESIGNS, N C .I 128Kx32 Battery Backed SRAM Module ADVANCED Features 128Kx32 bit CMOS Static Random Access Memory with on-board battery backup 128Kx32 Static RAM CMOS, High Speed Module The EDI8F32123C is a 4 megabit Battery Backed SRAM

socket am3 pinout

Abstract: socket AM2 pinout AM3 Processor Functional INTEL 80960 pipeline architecture 80960RM
Contextual Info: Intel 80960RM I/O Processor • ■ Complies with PCI Local Bus Specification, Revision 2.2 Universal 5 V and 3.3 V PCI Signalling Environment (C-stepping only) Data Sheet Product Features ■ ■ ■ ■ High Performance Intel® 80960JT Core ■ —Sustained One Instruction/Clock Execution

540L

Contextual Info: 80960RM I/O Processor • Complies with PCI Local Bus Specification, Revision 2.1 ■ 5 K PCI Signalling Environment Data Sheet Advance Information Product Features ■ High Performance 80960JT Core ■ — Sustained One Instruction/Clock Execution — 16 Kbyte, Two-Way Set-Associative

LGA 1155 Socket PIN diagram

Abstract: LGA 1155 PIN diagram LGA 1155 pin out lga1155 pin diagram E3-1275 intel LGA 1155 PIN diagram 1155 PINmap lga1155 land E3-1260L CATERR Catastrophic Error
Contextual Info: Intel Xeon® Processor E3-1200 Family Datasheet, Volume 1 This is Volume 1 of 2 June 2011 Document Number: 324970-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

S29WS256N

Abstract: S71WS512NE0BFWZZ
Contextual Info: S71WS512NE0BFWZZ Stacked Multi-Chip Product MCP Flash Memory and pSRAM CMOS 1.8 Volt, Simultaneous Operation, Burst Mode Flash Memory and Pseudo-Static RAM ADVANCE INFORMATION DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION MCP Features The S71WS512 Series is a product line of stacked Multi-Chip

MO-47AE

Abstract: ADSP-21060L ADSP-21062L EDI8L32128V EDI8L32512V MPC860 TMS320LC31
Contextual Info: EDI8L32512V White Electronic Designs 512Kx32 SRAM Module.3.3V FEATURES    ADSP-21060L SHARC  ADSP-21062L (SHARC)  Texas Instruments TMS320LC31   The EDI8L32512V is a high speed, 3.3V, 16 megabit SRAM. The device is available with access times of 12, 15, 17 and

100MHZ

Abstract: 133MHZ WED3DL644V
Contextual Info: White Electronic Designs WED3DL644V 4Mx64 SDRAM FEATURES DESCRIPTION The WED3DL644V is a 4Mx64 Synchronous DRAM configured as 4x1Mx64. The SDRAM BGA is constructed with four 4Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 153 lead, 17mm by

cmo 765

Abstract: GR-78 DDR200 DDR266A PC2100 10292003-DNYO-BD9L infineon ddr numbering
Contextual Info: Data Sheet, Rev. 1.2, Jan. 2004 HYS72D16500GR-[7/8]-A HYS72D32501GR-[7/8]-A Low Profile DDR SDRAM-Modules DDR SDRAM Memory Products N e v e r s t o p t h i n k i n g . The information in this document is subject to change without notice. Edition 2004-06 Published by Infineon Technologies AG,

Contextual Info: WEDPY256K72V-XBX 256Kx72 Synchronous Pipeline SRAM Preliminary* FEATURES DESCRIPTION n Fast clock speed: 100, 133, 150, 166 and 200* MHz The WEDPY256K72V-XBX employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. The 16Mb Synchronous SRAMs integrate

EDI8L32512V-AC

Abstract: EDI8L32128V EDI8L32512V MO-47AE MPC860 TMS320LC31 ADSP-21060L ADSP-21062L
Contextual Info: White Electronic Designs EDI8L32512V 512Kx32 SRAM Module.3.3V FEATURES DESCRIPTION DSP Memory Solution The EDI8L32512V is a high speed, 3.3V, 16 megabit SRAM. The device is available with access times of 12, 15, 17 and 20ns allowing the creation of a no wait state DSP and RISC

8l32128c

Abstract: block diagram of of TMS320C4X EDI8L32512C20AI EDI8L32512C TMS320C30 TMS320C32 DSP96002 EDI8L24128C EDI8L32256C
Contextual Info: EDI8L32512C 512K x 32 CMOS High Speed Static RAM FEATURES DESCRIPTION DSP Memory Solution • Motorola DSP96002 • Analog SHARC DSP • Texas Instruments TMS320C3x, TMS320C4x Random Access Memory Array • Fast Access Times: 12*, 15, 17, and 20ns • TTL Compatible Inputs and Outputs

IBM041841RLAD7

Abstract: IBM043641rLAD SA10 SA11 SA13 SA14 SA16 35 x 35 PBGA, 580 100 balls 4k sram
Contextual Info: . Preliminary IBM041841RLAD IBM043641RLAD 128K x 36 & 256K x 18 SRAM Features • 128K x 36 or 256K x 18 Organizations • CMOS Technology • Synchronous Pipeline Mode Of Operation with Self-Timed Late Write • Single Differential PECL Clocks compatible with

IBM043641WLAD-4

Abstract: IBM043641WLAD IBM043641WLAD3P IBM043641WLAD3 IBM043641WLAD-3P IBM043641WLA SA10 SA11 SA13 SA16
Contextual Info: . Preliminary IBM041841WLAD IBM043641WLAD 128K x 36 & 256K x 18 SRAM Features • 128K x 36 or 256K x 18 Organizations • CMOS Technology • Synchronous Pipeline Mode Of Operation with Self-Timed Late Write • Single Ended Pseudo-PECL Clock compatible with LVTTL Levels

SA73A

Contextual Info: . Preliminary IBM043611RLAB IBM041811RLAB 32K X 36 & 64K X 18 SRAM Features • 32K x 36 or 64K x 18 Organizations • Registered Outputs • 0.5 Micron CMOS Technology • Asynchronous Output Enable and Power Down Inputs • Synchronous Pipeline Mode Of Operation with

EDI8L32512V-AC

Abstract: 8L32512V
Contextual Info: EDI8L32512V 512Kx32 SRAM MODULE, 3.3V FEATURES The EDI8L32512V is a high speed, 3.3V, 16 megabit SRAM. The device is available with access times of 12, 15, 17 and 20ns allowing the creation of a no wait state DSP and RISC microprocessor memory solutions. • DSP Memory Solution

Contextual Info: . Preliminary IBM04184BSLAD IBM04364BSLAD 256K x 18 & 128K x 36 SW SRAM Features • 256K x 18 & 128K x 36 Organizations nous Select and Data Ins • CMOS Technology • Registered Outputs • Synchronous Pipeline Mode Of Operation with Standard Write • Asynchronous Output Enable and Power Down

Contextual Info: EDI8L32512C ^ E D I 512KX32 SRAM Module ELECTRONIC DESIGNS, INC 512Kx32 CMOS High Speed Static RAM Features DSP Memory Solution The EDI8L32512C is a highspeed, 5V, 16 megabit SRAM. The device is available with access times of 12,15,17 and 20ns allowing the creation of a no wait state DSP memory