Part Number
    Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    CPUA20 Search Results

    CPUA20 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    yg 2822

    Abstract: RAS 0510 cs8221 neat Waukesha 6670 82C631 82c211 2021G 82C206 CHIPset for 80286 REG62
    Contextual Info: PRELIM INARY C S 8221 NEW ENHANCED AT NEAT DATA BOOK 8 2 C 2 1 1 / 8 2 C 2 1 2 / 8 2 C 2 1 5 / 8 2 C 2 0 6 (IPC ) CHIPSet™ 100% IBM™ PC/AT Compatible New En­ hanced CHIPSet™ for 12MHz to 16MHz systems Supports 16MHz 80286 operation with only 0.5-0.7 wait states for 100ns DRAMs and 12


    OCR Scan     		CS8221 82C211 /82C212/82C215/82C206 12MHz 16MHz 100ns 150ns yg 2822 RAS 0510 cs8221 neat Waukesha 6670 82C631 2021G 82C206 CHIPset for 80286 REG62 PDF

    GC102

    Abstract: 8088 motherboard schematics ASC 8.000MHz crystal oscillator cpu 416-2 DP CQA03 coa030 sd 7406 ero 1818 74ALS245 TI HA 7406
    Contextual Info: G-TUO -CE} INC D 5 D E I 3 7 7 7 4 7 S OGGOOt ,4 S I i i u i u i 7v ; c i o 2 12/16MHz PC/AT Compatible C h ip set Features Description • Highly Integrated PC/AT Com­ patible Three Chip Set. The GC101/GC102 is a fully IBM PC/AT compatible chip set support­


    OCR Scan     		377747S 12/16MHZ 16MHz 12MHz GC101/GC102 16MHz. /RAS40 /RAS6080 RAS40 GC102 8088 motherboard schematics ASC 8.000MHz crystal oscillator cpu 416-2 DP CQA03 coa030 sd 7406 ero 1818 74ALS245 TI HA 7406 PDF

    T45 12H

    Abstract: memory decoding 80386dx 16 bit sl90 LIM EMS 4.0 N804CS
    Contextual Info: The FlexSet PC/AT 80386DX System & Memory Controller _ SL9352 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • • • • • • Synchronous or Asynchronous System Control Operation.


    OCR Scan     		80386DX SL9352 SL9352 T45 12H memory decoding 80386dx 16 bit sl90 LIM EMS 4.0 N804CS PDF

    386sx

    Abstract: 386sx chipset A21-A23 sl9350 CHIPset for 80286 via flexset SL9151
    Contextual Info: y/ a SL9250 80386SX Page Mode Memory Controller PRELIMINARY FEATURES • Supports 80386SX based AT Designs. • Up to 20 MHz Performance. • Enhanced Fast Page Mode DRAM Controller. • Supports 8 M byte of On-Board Memory. • Shadow RAM Feature. • Programmable Wait State Options.


    OCR Scan     		SL9250 80386SX imple12 A2-A16, A20GATE, CLK8042, ADD20, 386sx 386sx chipset A21-A23 sl9350 CHIPset for 80286 via flexset SL9151 PDF

    CHIPset for 80286

    Abstract: SL6003 A1719 logicstar TL4A sl6005
    Contextual Info: ADDRESS & DATA BUS BUFFERS SL6003, SL6004, SL6005 17 PC/A T COMPATIBLE CHIP-SET W PRELIMINARY The SL6003 provides address latches and control buffers for the PC / AT system. Control signals from the SL6001 are buffered by the SL6003 and tri-stated for the expansion and the I/O buses. This


    OCR Scan     		SL6003, SL6004, SL6005 SL6003 SL6001 68-pin SL6004 CHIPset for 80286 A1719 logicstar TL4A sl6005 PDF

    MMSP2

    Abstract: LCD 640X200 480x320 37XH cga to vga by pic LCD 480X320 CA24 CA25 MA11 SC300
    Contextual Info: ÉlanSC300 Microcontroller Programmer’s Reference Manual Rev. B, January 1996 A D V A N C E D M I C R O D E V I C E S  1995 by Advanced Micro Devices, Inc. Advanced Micro Devices reserves the right to make changes in its products without notice in order to improve design or performance characteristics.


    Original     		lanTMSC300 16-bit MMSP2 LCD 640X200 480x320 37XH cga to vga by pic LCD 480X320 CA24 CA25 MA11 SC300 PDF

    RTS5158

    Abstract: northbridge G41 se u10i layout GM965 28K1 IC NS0013 sla5t bga676 rtl8010 C1087
    Contextual Info: A B C D E X'TAL 14.318MHz Merom Processor System Power Rail Management Dual-Core CLOCK GEN ICS9LPR358AGLFT uFCPGA 478 2 3,4 FSB (667/800 MHz) FSB 4 GM965/PM965 ATI M74M USB 1 LVDS ＊V ＊VS HIGH HIGH ON ON ON ON S3 (Suspend to RAM) LOW HIGH HIGH HIGH ON


    Original     		318MHz ICS9LPR358AGLFT GM965/PM965 965GM 965PM 512MB 3B817 2R1066 74U23 76U23 RTS5158 northbridge G41 se u10i layout GM965 28K1 IC NS0013 sla5t bga676 rtl8010 C1087 PDF

    c106 1006

    Abstract: GC101-12 C144 sa 2n3904, itt GC101 41256 ram memory mapper A1723 GC101/GC102 GC101-16
    Contextual Info: GCIOI / GC102 12/16 MHZ PC/AT COMPATIBLE CHIP SET G2 Description Features • Highly integrated PC /A T compatible three chip set. • Supports up to 4 M eg D R A M using 1M or 256k devices. • Available in 16MHz and 12MHz ver­ sions. • Designed in CM OS for low power


    OCR Scan     		GC102 16MHz 12MHz GC101/GC102 16MHz. implemented/RAS100 /RAS100 c106 1006 GC101-12 C144 sa 2n3904, itt GC101 41256 ram memory mapper A1723 GC101-16 PDF

    t523

    Abstract: D8000H um82c210 UM82C212 registers OF 80286 bios call Unicorn Microelectronics
    Contextual Info: UNICORN MICROELECTRONICS TS7fl7flfl OOOOflOl Ü 2ME D UM82C212 Memory Controller U3V1C T ~ £ > -3 3 -3 1 2. UM82C212 MEMORY CONTROLLER The UM82C212 performs the memory control functions in the UM82C210 system. Several distinguished features are integrated in the UM82C212 that makes the


    OCR Scan     		UM82C212 T-W-35-21 UM82C210 t523 D8000H registers OF 80286 bios call Unicorn Microelectronics PDF

    82C211

    Abstract: 82c206 ipc P82C211 CS8221 82C206 E4000-H AT-286 S2-221-B CHIPset for 80286 82C215
    Contextual Info: CHIP S & T E C H N O L O G I E S INC Tû CHÏPS DE I SOTflllti ODDlOfiD fl T - 5Z-3 3 -0 5 PRELIMINARY CS8221 NEW ENHANCED AT NEAT DATA BOOK 82C211/8 2 C 2 1 2 /8 2 C 2 1 5 /8 2 C 2 0 6 (IPC) CHIPSet™ • 100% IBM7“ PC/AT Compatible New .En­ hanced CHIPSet™ tor 12MHz to 16MHz


    OCR Scan     		CS8221 82C211 /82C212/82C215/82C206 12MHz 16MHz 100ns 150ns 82c206 ipc P82C211 82C206 E4000-H AT-286 S2-221-B CHIPset for 80286 82C215 PDF

    T45 12H

    Abstract: 80386dx pipeline ROY TODD 80386DX 16 BIT Code T6S intel 80386dx 80386DX NBS16 sl9030 SL903
    Contextual Info: The FlexSet PC/AT 80386DX System & Memory Controller _ SL9352 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • Synchronous or Asynchronous System Control Operation. • Programmable Command Delays.


    OCR Scan     		80386DX SL9352 SL9352 T45 12H 80386dx pipeline ROY TODD 80386DX 16 BIT Code T6S intel 80386dx NBS16 sl9030 SL903 PDF

    80387

    Abstract: weitek 85C320 85C330 3i bios chip 80386 85C310 cache controller pipeline architecture for 80386 21U9
    Contextual Info: SIS 85C310 _ Cache/Memory Controller Rev 1.1 Preliminary FEATURES • 25/33MHz Non-Pipeline Operation • Built-in Direct Mapped Cache Controller for 32K/64K/128K/256K Cache or More


    OCR Scan     		85C310 25/33MHz 32K/64K/128K/256K 100-Pin 80387 weitek 85C320 85C330 3i bios chip 80386 85C310 cache controller pipeline architecture for 80386 21U9 PDF

    SA17

    Contextual Info: GICSTAR PAGE M O D E MEMORY CONTROLLER SL9350 PRELIMINARY FEATURES • 16,2 0 ,2 5 M H z O ptions. • E nhanced fast page m od e design. • Program m able w ait state options. • S h ad ow Ram feature. • Supports 16 M b yte o f on board m em ory. • Can u se 256K x 1, 1 M eg x 1,and 256K x 4 D R A M s or a m ix.


    OCR Scan     		SL9350 4160-B SL9350 0121iO SA17 PDF

    386SX

    Abstract: 5121M SL9010 D1384 intel 80386sx 80386SX 80386sx-based interleave SL9251 VIA SL9250
    Contextual Info: The FlexSet PC/AT 80386SX Page Interleave M em ory Controller SL9251 PRELIMINARY FEATURES • Supports 80386SX based AT D esigns. • Up to 20 M Hz Performance. • Enhanced Fast Page M ode/Page Interleave. • Supports 8 M bytes of On-Board Memory. • Shadow RAM Feature


    OCR Scan     		80386SX SL9251 512X512 SL9251 386SX 5121M SL9010 D1384 intel 80386sx 80386sx-based interleave VIA SL9250 PDF

    cd 1191 acb

    Abstract: crystal oscillator 8mhz ntk tl38a 82C356 SI-111J CS82310 387DX WK2C mip 2F3 82C351
    Contextual Info: PEAK/DM Data Book February 1991 Copyright Notio« Software Copyright ê 1991, CHIPS and Technologies, Inc. Manual Copyright 1991, CHIPS and Technologies, Inc. All Rights Reserved. P tizüed in U.S.A. Trademarks PEAK , PEAK/DM™ and PEAK/5X™ are trademarks ofCHIPS and Technologies,


    OCR Scan     		CS82310 386DXâ 387DXâ 9513d -DB04 012004-0M cd 1191 acb crystal oscillator 8mhz ntk tl38a 82C356 SI-111J 387DX WK2C mip 2F3 82C351 PDF

    T-538

    Abstract: K1557 82c311 82C316 i80387 LG variable frequency drive is3 82C811 hp 1502 vga 82c315 82C81
    Contextual Info: CS8233 PEAK/386 AT CHIPSet PEAK/386 AT December 1990 P R E L I M I N A R Y v -ir i i r b Copyright Notice Software Copyright 1990, CHIPS and Technologies, Inc. Manual Copyright © 1990, CHIPS and Technologies, Inc. a 11 r t J .1 r v ig U L » d _ v 6U .


    OCR Scan     		CS8233 PEAK/386 T-538 K1557 82c311 82C316 i80387 LG variable frequency drive is3 82C811 hp 1502 vga 82c315 82C81 PDF

    MSL9351

    Abstract: DI512 sl9350 sl90 SL9351 SL9010
    Contextual Info: The FlexSet PC/AT 80386DX Memory Controller _ SL9351 ADVANCED FEATURES • Supports 80386DX based AT Designs. • Up to 20 MHz Performance. • Enhanced Fast Page Mode/Page Interleave. • Supports 16 M bytes of On Board Memory. • Shadow RAM Feature


    OCR Scan     		80386DX SL9351 A2-A16, A20GATE, CLK8042, ADD20, NLDEC16, A17-A19, A21-A23, MSL9351 DI512 sl9350 sl90 SL9351 SL9010 PDF

    logical block diagram of 80286

    Abstract: TL4A A20GATE sl93 sl90 LIM EMS 4.0 SL9151
    Contextual Info: SL9151 80286 Page Interleave Memory Controller PRELIMINARY FEATURES • Supports 80286 based designs. • 16,20 or 25 MHz Options. • Enhanced Fast Page Mode/Page Interleave DRAM Controller. • Hardware support for EMS LIM 4.0 standard and EEMS. • Supports up to 8 M byte of on board memory.


    OCR Scan     		SL9151 120ns 25MHz. NRDY16 NCAS00-31 SL9151 logical block diagram of 80286 TL4A A20GATE sl93 sl90 LIM EMS 4.0 PDF

    vl82c10

    Contextual Info: VLSI T e ch n o lo g y, inc. ADVANCE INFORMATION VL82C315A SCAMP II SYSTEM CONTROLLER FEATURES • Compatible with 386SX-based PC/AT compatible systems. Also 386DX, 486SX, or 486DX via VL82C3216 Cache Controller and Interface Unit • Up to 33 MHz system clock in 5.0 V


    OCR Scan     		VL82C315A 386SX-based 386DX, 486SX, 486DX VL82C3216 82C37A 74LS612 82C59A 82C54 vl82c10 PDF

    Headland Technology Product Group

    Abstract: headland headland technology 80386 microprocessor pin out diagram GC205 M240-M241 CC182 logical block diagram of 80286 headland 386 SPA21
    Contextual Info: II GCK181 Universal PS/2 Chip Set Headland Technology Inc FEATURES d e s c r ip t io n • Universal Micro Channel Com­ patible chip set supporting the Intel 80286,386SX and 80386 to 25 MHz • Designed in 0.9 Micron channel length HCMOS and BiCMOS in Surface Mount Packages


    OCR Scan     		GCK181 386SX 20MHz 20MHz Headland Technology Product Group headland headland technology 80386 microprocessor pin out diagram GC205 M240-M241 CC182 logical block diagram of 80286 headland 386 SPA21 PDF

    T80-T

    Abstract: toggle switch t80-t sl9030 LIM EMS 4.0 80387SX de-nor intel 80386sx 80386SX L73H N804CS
    Contextual Info: The FlexSet PC/AT 80386SX System & M em ory Controller _ SL9252 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • Synchronous or Asynchronous System Control Operation.


    OCR Scan     		80386SX SL9252 T80-T toggle switch t80-t sl9030 LIM EMS 4.0 80387SX de-nor intel 80386sx L73H N804CS PDF

    lm385n

    Abstract: quanta computer F312V CB-145 MDB41 RTL8101L quanta foxconn CPU-A13 ics9541
    Contextual Info: 1 2 3 4 5 6 7 8 NT2A - Block Diagram AC/BATT CONNECTOR A PG 30 CPU Thermal Sensor NWD/PRESCOTT Clocking CPU CORE DC/DC CK-410 ISL6247 Max 1632 IO SC1486 A uFCPGA 478 Pins BATT CHARGER MAX1772 PG 30 PG 3 PG 3 PG 34,35 PG 29 PG 30,31 PG 2 LCD 17.0"/15.4" WXGA


    Original     		CK-410 ISL6247 SC1486 MAX1772 533/667/800MHz 64/128M) M24-P 333MHz SI4362DY IRF7811A lm385n quanta computer F312V CB-145 MDB41 RTL8101L quanta foxconn CPU-A13 ics9541 PDF

    VL82C102

    Abstract: vl82c102a-qc VL82C LA17-LA23 VL82C1 LM 4741 VL82C102aQC
    Contextual Info: VLSI T e c h n o l o g y , in c . VL82C102A PC/AT-COMPATIBLE MEMORY CONTROLLER FEATURES DESCRIPTION • Fully compatible with IBM PC/AT-type designs The VL82C102A PC/AT-Compatible Memory Controller generates the row and column decodes necessary to support the dynamic RAMs used in PC/


    OCR Scan     		VL82C102A VL82C102A 640k-bytes 100-PIN T-90-20 VL82C102 vl82c102a-qc VL82C LA17-LA23 VL82C1 LM 4741 VL82C102aQC PDF

    SiS 386

    Abstract: 80387 386 sis weitek 85C330 sis85
    Contextual Info: SIS 85C310 _ Cache/Memory Controller Rev 1.1 Preliminary FEATURES • 25/33MHz Non-Pipeline Operation • Built-in Direct Mapped Cache Controller for 32K/64K/128K/256K Cache or More


    OCR Scan     		85C310 25/33MHz 32K/64K/128K/256K SiS 386 80387 386 sis weitek 85C330 sis85 PDF