B3S33TL Search Results
B3S33TL Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: nOSEL-VITELIC bSE ]> • b3S33Tl G0 Dlfl2ö b?b M M O V I V53C256A FAMILY HIGH PERFORMANCE, LOW POWER 2 5 6 K X 1 BIT FAST PAGE MODE CMOS DYNAMIC RAM MOSEL- VITELIC H IG H P E R F O R M A N C E V 5 3 C 2 5 6 A 6 0 /6 0 L 7Q /70L 8 0 /8 0 L 1 0 /1 0 L 60 ns |
OCR Scan |
b3s33tlv53c256a | |
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Contextual Info: MOSEL — VITELIC 4flE D MOSEL b3S33Tl Q O Q O i m MOVI 5 MS72215/16 & MS72225/26 ADVANCE INFORMATION 512 x 18 & 1024 x 18 Parallel Synchronous FIFOs FEATURES DESCRIPTION • Full C M O S clocked synchronous FIFO s The MS72215/16 and MS72225/26 are clocked registered FIFOs |
OCR Scan |
b3s33tlms72215/16ms72225/2618-bit | |
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Contextual Info: S4E D b3S33Tl DGQlbMB 1Ö4 MOSEL MS318000 ADVANCE INFORMATION 512K x 16,1 MEG x 8 CMOS Mask Mask Programmable ROM f! OSEL - VI T EL IC FEATURES The MS318000 is an 8 Mb CMOS Slgate maskprogrammable static read only memory organized as 524,288 words by 16 bits or 1,048,576 words by 8 |
OCR Scan |
b3s33tlms318000200ns | |
386dx bios
Abstract: Non VGA Video Controller IC 486DX 486SX
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OCR Scan |
b3s33tlddd171d10sel-vitelicms400+5 | |
MS628128Contextual Info: MOSEL-VITELIC fc,2E ]> MOSEL-VITELIC • b3S33Tl QQQ25Q7 OTh ■ UOVI MS628128 1048576 131,072 x 8 CMOS STATIC RAM WITH DATA RETENTION AND LOW POWER ADVANCED INFORMA TION Features Description ■ Available in 8 0 /100/120 ns (Max.) ■ Automatic power-down when chip disabled |
OCR Scan |
b3s33tlqqq25q7ms628128s628128+6 | |
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Contextual Info: MOSEL-VITELIC bSE J> m M O S E L -V IT E L IC bBSBBTl ÜDD24Db 27e! « M O V I V404J232and V404J236 2M x 32 and 2M x 36 CMOS MEMORY MODULES PRELIMINARY Features Description • ■ ■ ■ ■ ■ The V404J232 memory Module is organized as 2,097,152 x 32 bits in a 72-lead single-in-line mod |
OCR Scan |
v404j232andv404j236dd24db72-lead+3 | |
7202AContextual Info: M OSEL V ITEU C MS7200U7201AL/7202AL 256x9,512x9, 1Kx9 CMOS FIFO Features Descriptions • First-In/First-Out static RAM based dual port memory ■ Three densities in a x9 configuration ■ Low power versions ■ Includes empty, full, and half full status flags |
OCR Scan |
ms7200u7201al/7202al256x9512x9ms7200l/7201al/7202al+7 | |
led flasher
Abstract: T-77-13
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OCR Scan |
00d1lmss0581pid201b3s33+5 | |
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Contextual Info: M O SEL VITELIC V53C311616500 3.3 VOLT 1 M X 16 EDO PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE 50 60 70 Max. RAS Access Time, Irac 50 ns 60 ns 70 ns Max. Column Address Access Time, (^ aa) 25 ns 30 ns 35 ns Min. Extended Data Out Page Mode Cycle Time, fcc) |
OCR Scan |
v53c31161650016-bitcycles/6442-pin+3 | |
45l50
Abstract: V53C104H
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OCR Scan |
v53c104h45/45l50/50l55/55l+6 | |
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Contextual Info: M O S E L VÊTEL IC V53C8256H U LTR A -H IG H PERFO RM ANCE, L O W PO W ER 2 5 6 K X 8 B IT F A S T P A G E M O D E CM O S D YN A M IC R A M H IG H P E R F O R M A N C E Max. RAS Access Time, tRAC 4 5 /4 5 L 5 0 /5 0 L 5 5 /5 5 L 6 0 /6 0 L 45 ns 50 ns 55 ns |
OCR Scan |
v53c8256h115ns8256h | |
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Contextual Info: M O SE L VÊTELIC V53C404B HIGH PERFORMANCE, LOW POWER 1 M X 4 BIT FAST PAGE MODE CMOS DYNAMIC RAM 60 70 80 10 M ax. RAS Access Time, 1RAC 60 ns 70 ns 80 ns 100 ns M ax. Column Address Access Tim e, (tCAA) 30 ns 35 ns 40 ns 50 ns HIGH PERFORMANCE V53C404B |
OCR Scan |
v53c404b404b-10 | |
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Contextual Info: M OSEL VITELIC V53C8125H ULTR A -H IG H PERFORM ANCE, 128K X 8 B IT F A S T P A G E M O D E CM OS D Y N A M IC R A M HIGH PERFORMANCE P R E LIM IN A R Y 35 40 45 50 Max. RAS Access Time, tRAC 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (tç^A) |
OCR Scan |
v53c8125h24-pin26/24-pin000355b | |
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Contextual Info: M O S E L V IT E L IC V53C8257H U LTR A -HIG H SPEED, 256KX 8B IT P A G E M O D E WITH E X TE N D E D DATA O U T P U T ED O A N D C A S B U R S T M O D E CM O S D YN A M IC R A M PR E LIM IN A R Y 45/45L 50/50L 55/55L 60/60L Max. RAS Access Time, Orac) |
OCR Scan |
v53c8257h256kx45/45l50/50l+3 | |
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Contextual Info: M O SE L VITELIC PRELIMINARY V62C518256 32Kx8 BIT STATIC RAM Features Description • High-speed: 35,45, 55, 70 ns ■ Ultra low DC operating current of 5mA Max. ■ Low Power dissipation: TTL Standby: 3mA (Max.) CMOS Standby: 20n.A (Max.) ■ Fully static operation |
OCR Scan |
v62c51825632kx828-pin144-bit+1 | |
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Contextual Info: M O S E L V IT E L IC V53C16256L 3.3 VOLT 2 5 6 K X 16 FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 40 45 50 60 Max. RAS Access Time, tpAo 40 ns 45 ns 50 ns 60 ns Max. Column Address Access Time, (fc/vO 20 ns 22 ns 24 ns 30 ns Min. Fast Page Mode Cycle Time, (tpC) |
OCR Scan |
v53c16256l16-bitb3s33tl | |
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Contextual Info: M O SEL VTTEUC PRELIMINARY V104J232 512K x 32 SIMM Features Description 524,288 x 32 bit organizations Utilizes 256K x 4 CMOS DRAMs Fast access times 70 ns, 80 ns, 100 ns Fast Page mode operation Low power dissipation _ CAS before RAS refresh, RAS only refresh, and |
OCR Scan |
v104j23272-leaddd03350 | |
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Contextual Info: M O S EL V IT E L IC V53C8129H ULTRA-HIGH PERFORMANCE, 128K X 8 BIT EDO PAGE MODE CMOS DYNAMIC RAM PRELIMINARY 35 40 45 50 Max. RAS Access Time, tRAC 35 ns 40 ns 45 ns 50 ns Max. Column Address Access Time, (Icu ò 18 ns 20 ns 22 ns 24 ns Min. Fast Page Mode With EDO Cycle Time, (tpC) |
OCR Scan |
v53c8129hv53c8129h-5024-pin26/24-pin+1 | |
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Contextual Info: M O S EL V IT E L IC V53C511816502 1M x 16 EDO PA G E M ODE CMOS DYNAM IC RAM OPTIONAL SE LF REFRESH HIGH PERFORMANCE 50 60 Max. RAS Access Time, Jrac 50 ns 60 ns Max. Column Address Access Time, (^;aa ) 25 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (1pC) |
OCR Scan |
v53c51181650216-bitcycles/1642-pin+2 | |
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Contextual Info: M O SEL VITELIC PREW BBtO M V62C51864 8Kx8 B IT STA TIC RAM Features Description • ■ ■ The V 62C 51864 is a 65,536-bit static random access memory organized as 8,192 words by 8 bits. It is built with M O SE L VITE LIC ’s high performance C M O S process. Inputs and three state outputs are |
OCR Scan |
v62c51864536-bitb353328-pin | |
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Contextual Info: MOSEL VITELIC P R E LIM IN A R Y V53C16256H 2 5 6 K X 16 F A S T P A G E M O D E CM O S D YN A M IC R A M HIGH PERFORMANCE 40 45 50 60 40 ns 45 ns 50 ns 60 ns 20 ns 22 ns 24 ns 30 ns Min. Fast Page Mode Cycle Time, tPC 23 ns 25 ns 28 ns 35 ns Min. Read/Write Cycle Time, (tRC) |
OCR Scan |
v53c16256h110nsl3s331140-pin+2 | |
ULTRA HQX
Abstract: MS62256L-10 MS62256 MS62256L-12 MS62256L-70 MS62256L-70FC MS62256L-85 T-46 ms62256l-70pc MS62256L10PC
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OCR Scan |
b3533tlddd13tms62256ms62256l+13 | |
v110h
Abstract: V53C104F
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OCR Scan |
v53c104f60/60l70/70l80/80l+6 | |
kexzContextual Info: MOSEL-VITELIC b2E » MOSEL-VITELIC • b3533Tl GGGS33L. GES ■ M O V I V104J232, V104J236 512K X 32, 512K x 36 SIMM PRELIMINARY Features Description a 524,288 x 32 bit or 524,288 x 36 bit The V104J232 Memory Module is organized as 524,288 x 32 bits in a 72-lead single-in-line module. |
OCR Scan |
b3533tlgggs33lv104j232v104j236+4 | |