ACT112 Search Results

transistor AC126

Abstract: equivalent transistor ac125 AC393 AC126 74AC393 AC365 AC682 d flip flop p6nk60z ACT03
Contextual Info: HC Portfolio Comparison PART # AC00 ACT00 AC01 AC02 ACT02 AC03 ACT03 AC04 ACT04 ACU04 AC05 ACT05 AC07 AC08 ACT08 AC09 AC10 ACT10 AC11 ACT11 AC14 ACT14 AC20 ACT20 AC32 ACT32 AC74 ACT74 AC86 ACT86 AC107 AC109 ACT109 AC112 ACT112 AC123 AC125 ACT125 AC126 ACT126

AC1123

Abstract: 74AC11239
Contextual Info: 74AC/ACT11239 Signetics Dual 2-to-4 Line D ecoder/ Demultiplexer; Active-High AC11239: Product Specification ACT11239: Objective Specification ACL Products GENERAL INFORMATION FEATURES C O N D IT IO N S • Demultiplexing capability • Two Independent 1-of-4 decoders

Contextual Info: 74AC/ACT11250 Signetics 16-Input Multiplexer 3-State , Inverting Objective Specification ACL Products GENERAL INFORMATION FEATURES • Output capability: ±24 mA • CMOS (AC) and TTL (ACT) voltage level inputs Propagation delay • 5 0 0 incident wave switching

Contextual Info: ACT112 ACT112 Dual JK Negative Edge-Triggered Flip-Flop Literature Number: SNOS434A July 20, 2009 ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 'ACT112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state

Contextual Info: Technical Data „ , CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/ACT112 Advanced Information Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features:

Contextual Info: Technical Data , CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/ACT112 Advanced Informaron Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features: • Buffered inputs

315 sum lf

Abstract: 74AC11286 74AC11286D 74AC11286N 74ACT11286 74ACT11286D 74ACT11286N
Contextual Info: Philips Components— Signetics 74AC/ACT11286 Document No. 853-1496 ECN No. 00731 Date of Issue October 17, 1990 Status Product Specification 9-bit odd/even parity generator/ checker with bus drive I/O port ACL Products QUICK REFERENCE DATA FEATURES • Generates either odd or even parity

J112 in smd

Abstract: smd transistor kn 54ACT112 54ACT112DMQB 54ACT112FMQB 54ACT112LMQB ACT112 J112
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 07/02/96 Last Update Date: 03/17/97 Last Major Revision Date: 02/05/97 ACT112-X REV 2A0 Dual JK Negative Edge-Triggered Flip-Flop General Description The ACT112 contain two Independent, high-speed JK flip-flops with Direct Set and Clear

74AC11258

Contextual Info: 74AC/ACT11258 Signetics Quad 2-Input Multiplexer 3-State , Inverting P roduct Specification ACL Products FEATURES GENERAL INFORMATION • Output capability: ±24 mA UNIT il o o ; Propagation delay n l0> to nY , PLH/ 'PHL C L - 50pF Power dissipation capacitance por

Contextual Info: HD74AC112/ACT112-S-VCw,',Eda'Tr""*'*d Description The HD7 4 AC112/HD74 ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when

Contextual Info: 74AC/ACT11241 Signetics Octal Buffer/Line Driver; 3-State Product Specification ACL Products GENERAL INFORMATION FEATURES CONDITIONS • Octal bus interface PARAMETER SYMBOL • 3-State buffers • Output capability: ±24 mA • CMOS AC and TTL (ACT) voltage

74ac109

Abstract: 74ac112
Contextual Info: Technical Data . CD54/74AC109, CD54/74AC112 CD54/74ACT109, CDS4/ACT112 Advanced Intorniai,on U - î — Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112- Negative-Edge-Triggered (J, K) 3 2S -

74AC112

Contextual Info: CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/ACT112 Advanced Information Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features: G ND s 8 • B uffered inputs

national semiconductor databook

Abstract: 54ACT112 ACT112 E20A J16A W16A
Contextual Info: July 20, 2009 ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 'ACT112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly

Contextual Info: ACT11241, ACT11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0073— D2957 JULY 1987— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54A C T 11241 . . . J T P ACKA G E 74A C T11 2 41 . . . D W OH N T P ACKA G E • 3-State Outputs Drive Bus Lines or Buffer

specifications of transistor AC126

Abstract: hc132a hc138a specifications of AC126 HC74A TC7PGU04FU transistor AC126 hc273a -toshiba toshiba vhc32 TC4W53FU
Contextual Info: SEMICONDUCTOR GENERAL CATALOG General-Purpose Logic ICs CMOS Logic ICs Low-Voltage CMOS Logic ICs CMOS Logic ICs in Ultra-Small US Packages Dual-Supply Level Shifters CMOS Bus Switch ICs Application-Specific Logic One-Gate CMOS L-MOS 1 2009-8 SCE0004I CMOS Logic ICs (74AC, 74VHC, 74HC and Standard Series) Quick Reference

74 Series Logic ICs

Abstract: transistor AC126 74HC octal bidirectional latch cx 4060 8pin hc257a TC7PG17AFE TC7SG07FE Transistor 123AP AC139 hc11a
Contextual Info: General-Purpose Logic ICs CMOS Logic ICs z 94 Low-Voltage CMOS Logic ICs z 100 CMOS Logic ICs in Ultra-Small US Packages z 104 Dual-Supply Level Shifters z 106 CMOS Bus Switch ICs z 108 Application-Specific Logic z 110 One-Gate CMOS L-MOS z 112 89 CMOS Logic ICs (74AC, 74VHC, 74HC and Standard Series) Quick Reference

Contextual Info: Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/ACT112 Tf x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC H S282 IS- » 2 1JÎK IC f*ÎR • 3 4 1 1 • IO Dual “J-K” Flip-Flop with Set and Reset F /F 1 CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

Contextual Info: ACT112, ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 D D D D D D ACT112 . . . F PACKAGE ACT112 . . . M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With

Contextual Info: ACT11241, ACT11241 OCTAL BUFFERS/LINE DRIVERS WITH 3ĆSTATE OUTPUTS ą SCAS011B − D2957, JULY 1987 − REVISED APRIL 1993 • • • • • • • ACT11241 . . . JT PACKAGE ACT11241 . . . DB, DW OR NT PACKAGE 3-State Outputs Drive Bus Lines or Buffer

74AC11240N

Abstract: act11240
Contextual Info: 74AC/ACT 11240 Signetics O ctal Buffer/Line Driver; 3-State; INV Product Specification ACL Products GENERAL INFORMATION SYMBOL • Output capability: ±24 mA Propagation delay A to Y PLH • CMOS AC and TTL (ACT) voltage level inputs Power dissipation capacitance per

74AC11238

Contextual Info: 74AC/ACT 11238 Signetics 3-to-8 Line D ecoder/ Demultiplexer Product Specification ACL Products GENERAL INFORMATION FEATURES • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Non-Inverting outputs SYMBOL w l PHL CPD

ACT512

Abstract: ACT212 ACT112
Contextual Info: CT ULTRA SMALL AUTOMOTIVE RELAY 17.4 .685 CT-RELAYS FEATURES 14 .551 13.5 .531 Twin type 8 terminals 7.2 .283 17.4 .685 • Simple footprint enables ease of PC board layout • Ultra small size Twin type: 17.4(L)x14.0(W)x13.5(H)mm .685(L)x.551(W)x.531(H)inch

Contextual Info: ACT11241, ACT11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS011B - D2957, JULY 1987 - REVISED APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers ACT11241 . . . JT PACKAGE ACT11241 . . . DB, DW OR NT PACKAGE 1