74AC112 Search Results

D2957

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 74AC11204 HEX INVERTER/CLOCK DRIVER D3427, O C TO B ER 1989 DW OR N PACKAGE Low-Skew Propagation Delay Specifications for Clock Driver Applications TOP VIEW 1Y[ 1 2Y [ 2 3Y [ 3 Flow-Through Architecture Optimizes PCB Layout * * * Package Options Include Plastic “Small

Contextual Info: 74AC11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS SCAS448A – MAY 1987 – REVISED APRIL 1996 D D D D D DB, DW, OR NT PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

19ba

Contextual Info: 54AC11238, 74AC11238 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D3103. APRIL 1988 - REVISED APRIL 1993 * * * * * * * * Designed Specifically for High-Speed Memory Decoders and Data Transmission

Contextual Info: 74AC11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS010B – JULY 1987 – REVISED APRIL 1996 D D D D D D DB, DW, NT, OR PW PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: 54AC11245, 74AC11245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS _ P2957, JULY 1987 - REVISED APRIL 1993 54AC11245 . . . JT PACKAGE 74AC11244. . . DB, DW, NT, OR PW PACKAGE 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes

PHL 99

Contextual Info: 74AC11280 9-BIT PARITY GENERATOR/CHECKER _ SCAS055A - D3201, APRIL 1989 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW * Generates Either Odd or Even Parity for Nine Data Unes * Cascadable for n-BKs Parity B[ A[ £ ODD [ GND [ 2 EVEN [ NC [ ll * Flow-Through Architecture to Optimize

Contextual Info: Technical Data CD54/74AC109, CD54/74AC112 CD54/74ACT109, CD54/74ACT112 Tf x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC H S282 IS- » 2 1JÎK IC f*ÎR • 3 4 1 1 • IO Dual “J-K” Flip-Flop with Set and Reset F /F 1 CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

Contextual Info: 74AC11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS01 OB - JULY 1987 - REVISED APRIL 1996 3-State Outputs Drive Bus Lines Directly DB, DW, NT, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout A1 [ 1 Center-Pin V^c and GND Configurations

Contextual Info: 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171 B - MARCH 1987 - REVISED SEPTEMBER 1998 EPIC Enhanced-Performance Implanted CMOS 1- u r n Process DB, DW, NT, OR PW PACKAGE (TOP VIEW) 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

Contextual Info: 74AC11273 OCTAL DĆTYPE FLIPĆFLOP WITH CLEAR ą SCAS497 − D3442, MARCH 1990 − REVISED APRIL 1993 • • • • • • DW OR NT PACKAGE TOP VIEW Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Flow-Through Architecture to Optimize

Contextual Info: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3ĆSTATE OUTPUTS ą SCAS032A − JULY 1987 − REVISED APRIL 1993 • • • • • • 54AC11241 . . . JT PACKAGE 74AC11241 . . . DB, DW OR NT PACKAGE 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

CDC204

Abstract: MS-013
Contextual Info: CDC204 HEX INVERTER/CLOCK DRIVER SCAS098E – OCTOBER 1989– REVISED OCTOBER 1998 D D D D D D D D DW PACKAGE TOP VIEW CDC204 Replaces 74AC11204 Low-Skew Propagation Delay Specifications for Clock-Driver Applications CMOS-Compatible Inputs and Outputs Flow-Through Architecture Optimizes

74AC11257

Contextual Info: 74AC11257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS SCAS049B – MARCH 1989 – REVISED JUNE 1996 D D D D D D D 3-State Outputs Interface Directly With System Bus Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 D D D D D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB

Contextual Info: 74AC11280 9-BIT PARITY GENERATOR/CHECKER SCAS055A – D3201, APRIL 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Parity Flow-Through Architecture to Optimize

CDC203

Abstract: CDC203DW CDC203DWR CDC203DWRG4 MS-013
Contextual Info: CDC203 3.3-V HEX INVERTER/CLOCK DRIVER SCAS324A – OCTOBER 1989 – REVISED NOVEMBER 1995 D D D D D D D D DW PACKAGE TOP VIEW Replaces 74AC11203 Low-Skew Propagation Delay Specifications for Clock Driver Applications Operates at 3.3-V VCC Flow-Through Architecture Optimizes

74AC11251

Contextual Info: 74AC11251 1–OF–8 DATA SELECTOR/MULTIPLEXER WITH 3–STATE OUTPUTS SCAS085A – DECEMBER 1989 – REVISED APRIL 1993 • • • • • • • • D OR N PACKAGE 3-State Outputs Interface Directly with System Bus TOP VIEW Performs Parallel-to-Serial Conversion

54AC11253

Abstract: 74AC11253
Contextual Info: 54AC11253, 74AC11253 DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS041A – MAY 1988 – REVISED APRIL 1993 • • • • • • 54AC11253 . . . J PACKAGE 74AC11253 . . . D OR N PACKAGE TOP VIEW Permits Multiplexing From N Lines to

1B19-2-A

Abstract: 74AC11258
Contextual Info: 74AC11258 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER WITH 3-STATE OUTPUTS SCAS063A – D3257, JANUARY 1989 – REVISED APRIL 1993 • • • • • • • 3-State Outputs Interface Directly With System Bus Flow-Through Architecture to Optimize

Contextual Info: 54AC11238, 74AC11238 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS ą ą SCAS039A − APRIL 1988 − REVISED APRIL 1993 • • • • • • • Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Noninverting Version of ′AC11138

Contextual Info: 74AC11244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS171B – MARCH 1987 – REVISED SEPTEMBER 1998 D D D D D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB

Contextual Info: 74AC11353 DUAL 1 -0 R -4 DATA SELECTOR/MULTIPLEXER SCAS044A-JUNE 1 9 8 8- REVISED APRIL 1993 • • • Inverting Version of 74AC11253 Permits Multiplexing from N Lines to 1 Line Performs Parallel-to-Serial Conversion • Flow-Through Architecture Optimizes PCB

Contextual Info: 74AC11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS010B – JULY 1987 – REVISED APRIL 1996 D D D D D D DB, DW, NT, OR PW PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations