ACT109 Search Results

Contextual Info: Technical Data CD54/74AC109, CD54/74AC112 CD54/ACT109, CD54/74ACT112 Tf x a s In s t r u m e n t s Data sheet acquired from Harris Sem iconductor SC H S282 IS- » 2 1JÎK IC f*ÎR • 3 4 1 1 • IO Dual “J-K” Flip-Flop with Set and Reset F /F 1 CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

transistor AC126

Abstract: equivalent transistor ac125 AC393 AC126 74AC393 AC365 AC682 d flip flop p6nk60z ACT03
Contextual Info: HC Portfolio Comparison PART # AC00 ACT00 AC01 AC02 ACT02 AC03 ACT03 AC04 ACT04 ACU04 AC05 ACT05 AC07 AC08 ACT08 AC09 AC10 ACT10 AC11 ACT11 AC14 ACT14 AC20 ACT20 AC32 ACT32 AC74 ACT74 AC86 ACT86 AC107 AC109 ACT109 AC112 ACT112 AC123 AC125 ACT125 AC126 ACT126

74AC109

Abstract: 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC
Contextual Info: Revised November 1999 74AC109 • ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock

S35R2

Abstract: 1278n 74aC-aCT109 CD541 j8332 RCA
Contextual Info: HARRIS SEMICOND SECTOR 37E D • 4302271 D025411 6 *HAS _ Technical Data CD54/74AC109, CD54/74AC112 CD54/ACT109, CD54/74ACT112 Advanced Information 07 Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

Contextual Info: 43G2271 D G 2 S 4 H 37E D HARRIS SEMICOND SECTOR _ ñ *HAS Technical Data CD54/74AC109, CD54/74AC112 CD54/ACT109, CD54/74ACT112 Advanced Information T^fc-or?- 0 7 Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

Contextual Info: s e m ic o n d u c t o r Revised November 1999 74AC109 • ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two_ high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock

Contextual Info: AC109 • ACT109 54AC/74AC109 • 54ACT/ACT109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flipflops. The clocking operation is independent of

74AC109MTC

Abstract: 74AC109 74AC109PC 74AC109SC 74AC109SJ 74ACT109 74ACT109SC
Contextual Info: Revised August 2000 74AC109 • ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description Features The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock

74AC109

Abstract: 74AC109MTC 74ACT109 74AC109SC 74AC109SJ 74ACT109PC 74ACT109SC
Contextual Info: 74AC109, ACT109 Dual JK Positive Edge-Triggered Flip-Flop tm Features General Description • ICC reduced by 50% The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the

Contextual Info: Technical Data „ , CD54/74AC109, CD54/74AC112 CD54/ACT109, CD54/74ACT112 Advanced Information Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features:

Contextual Info: Technical Data , CD54/74AC109, CD54/74AC112 CD54/ACT109, CD54/74ACT112 Advanced Informaron Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features: • Buffered inputs

54ACT109

Abstract: 54ACT109DMQB 54ACT109FMQB 54ACT109LMQB ACT74 J109
Contextual Info: MICROCIRCUIT DATA SHEET Original Creation Date: 07/02/96 Last Update Date: 03/17/97 Last Major Revision Date: 02/05/97 ACT109-X REV 2A0 Dual JK Positive Edge-Triggered Flip-Flop General Description The ACT109 consists of two high-speed completely independent transition clocked

74AC109SC

Abstract: 74AC109 74AC109PC 74AC109SJ 74ACT109 74ACT109PC 74ACT109SC
Contextual Info: Revised October 1998 74AC109 • ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to CD Clear sets Q to LOW level The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking

rca 1967

Abstract: 74AC112
Contextual Info: Technical Data CD54/74AC109, CD54/74AC112 CD54/ACT109, CD54/74ACT112 v Texas In s t r u m e n t s D ata sheet acquired from Harris Sem iconductor SC H S282 u- Dual “J-K” Flip-Flop with Set and Reset F /F 1 IC P - 2S — 3C P 13 ia CD54/74AC/ACT109 - Positive-Edge-Triggered J, K

74ac109

Abstract: 74ac112
Contextual Info: Technical Data . CD54/74AC109, CD54/74AC112 CD54/ACT109, CDS4/74ACT112 Advanced Intorniai,on U - î — Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112- Negative-Edge-Triggered (J, K) 3 2S -

Contextual Info: 74AC109, ACT109 Dual JK Positive Edge-Triggered Flip-Flop tm Features General Description • ICC reduced by 50% The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the

74AC112

Contextual Info: CD54/74AC109, CD54/74AC112 CD54/ACT109, CD54/74ACT112 Advanced Information Dual “J-K” Flip-Flop with Set and Reset CD54/74AC/ACT109 - Positive-Edge-Triggered J, K CD54/74AC/ACT112 - Negative-Edge-Triggered (J, K) Type Features: G ND s 8 • B uffered inputs

ACT109

Abstract: ACT74
Contextual Info: AC109 • ACT109 54AC/74AC109 • 54 ACT/74 ACT 109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flipflops. The clocking operation is independent of

Contextual Info: AC109 • ACT109 5 4 A C /7 4 A C 1 0 9 • 5 4 A C T /7 4 A C T 1 0 9 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of tw o high-speed completely Independent transition clocked JK flipflops. The clocking operation Is independent of

CD54ACT109

Abstract: CD54ACT109F3A CD74ACT109 CD74ACT109E CD74ACT109M CD74ACT109M96
Contextual Info: ACT109, ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 D D D D D D ACT109 . . . F PACKAGE ACT109 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With

CD54ACT109

Abstract: CD54ACT109F3A CD74ACT109 CD74ACT109E CD74ACT109M CD74ACT109M96
Contextual Info: ACT109, ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 D D D D D D ACT109 . . . F PACKAGE ACT109 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With

948F

Abstract: MC74AC109 MC74AC109D MC74AC109N MC74ACT109 MC74ACT109D MC74ACT109N
Contextual Info: MC74AC109, ACT109 Dual JK Positive Edge−Triggered Flip−Flop The MC74AC109/ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform.

CD74AC648

Abstract: CD74ACT109E CD74ACT648 CD74AC7060E CD74ACT651 SSI 280 CD74AC191 CD74AC651
Contextual Info: Product Selectors Index to Devices 4 CMOS-Compatible Logic Plastic Pkg.t C h ipt CD74ACOOE/M CD54AC00H CD74AC02E/M CD54AC02H CD74AC04E/M CD54AC04H CD74AC05E/M CD54AC05H TTL-Compatible Logic Chip t Plastic Pkg.t CD74ACT00E/M CD54ACTOOH CD74ACT02E/M CD54ACT02H

Contextual Info: Advanced CM OS Logic Advanced CMOS Logic, ACL, is the next step forward in the evolution of CMOS logic. It matches bipolar FAST* in speed, performance and logic type output drive, but at CMOS power levels. Just as HC/HCT high-speed CMOS logic became an indus­