CD74AC648
Abstract: CD74ACT109E CD74ACT648 CD74AC7060E CD74ACT651 SSI 280 CD74AC191 CD74AC651
Text: MSI MSI 260 260 280 280 SSI 95 MSI MSI MSI MSI MSI MSI MSI MSI MSI MSI MSI MSI 206 294 300 307 300 307 , 267 274 274 280 287 280 287 Description Quad 2-Input NAND Gate Quad 2-Input NOR Gate Hex Inverter , 335 FF FF FF MSI MSI MSI MSI MSI MSI MSI 109 119 119 170 176 230 267 267 287 287 SSI SSI MSI MSI MSI MSI MSI 82 82 200 200 200 274 274 SSI SSI SSI 86 105 115 Function/Description NAND/NOR Gates SSI SSI SSI SSI 74 78 90 100 Classification Page 6 Product Selectors Product Selection Guide (Cont'd
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CD74ACOOE/M
CD54AC00H
CD74AC02E/M
CD54AC02H
CD74AC04E/M
CD54AC04H
CD74AC05E/M
CD54AC05H
CD74AC08E/M
CD74AC10E/M
CD74AC648
CD74ACT109E
CD74ACT648
CD74AC7060E
CD74ACT651
SSI 280
CD74AC191
CD74AC651
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SSI 280
Abstract: hard disk read channel 32P4105A viterbi
Text: Abridged Version SSI 32P4105A 280 Mbit/s PRML Read Channel with EPR4, 16/17 (0,6/8) ENDEC , Reference LI SI SSI 32P4105A 280 Mbit/s PRML Read Channel with EPR4, 16/17 (0,6/8) ENDEC BLOCK , $ TT2 TAD SSI 32P4105A 280 Mbit/s PRML Read Channel with EPR4, 16/17 (0,6/8) ENDEC FILTER , · Register programmable data rates from 100 to 280 Mbit/s · Programmable, symmetric , AUTOMATIC GAIN CONTROL The SSI 32P4105A utilizes an advanced BiCMOS process technology along with
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32P4105A
100-pin
SSI 280
hard disk read channel
32P4105A
viterbi
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Not Available
Abstract: No abstract text available
Text: MmMkms' A TDK Group/Company DESCRIPTION The SSI 67F686 Automobile Bus Transceiver is an analog , applications requiring pulse shaping, signal filtering, or transient detection. The SSI 67F686 allows a host , application and multi plexed data bus. The SSI 67F686 provides a waveshaped 7.75V bus waveform in response to , system with either a filtered or unfiltered logic signal. Automobile Bus Transceiver SSI 67F686 , procedures necessary for a static sensitive component. SSI 67F686 Automobile Bus Transceiver
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67F686
J1850
18-pin
67F686-P
67F686-P
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Not Available
Abstract: No abstract text available
Text: Absolute encoders - SSI Shaft ø10 mm with clamping lange Magnetic multiturn encoders 12 bit ST / 13 bit MT BMMV 58 SSI - MAGRES hermetic Features â Encoder multiturn / SSI â Magnetic , BMMV 58K SSI with clamping lange Technical data - electrical ratings Technical data - mechanical , 69K Interface SSI Operating speed â¤6000 rpm Function Multiturn Stainless steel , sense of rotation (looking at lange) Inputs SSI clock Reset input Output circuit SSI data
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tape head preamp circuit ssi
Abstract: P3216 DP 804 C "tape storage" jwc 251
Text: ABRIDGED 1 VERSION SSI 34P3216A m A TDK Group/Company m s u s im Read Pream p/Channel fo r Tape Storage Advance Information February 1996 DESCRIPTION The SSI 34P3216A is a high , . Programmable functions of the SSI 34P 3216A de vice are co n tro lle d through a b i directional serial port and banks of internal registers. The SSI 34P3216A utilizes an advanced BiCMOS process technology along , consumption. The SSI 34P3216A supports a sleep mode for minimal power dissipation In non-operational periods
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34P3216A
34P3216A
tape head preamp circuit ssi
P3216
DP 804 C
"tape storage"
jwc 251
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SSI 280
Abstract: ST506 32B545
Text: M m M Ím s ' SSI 32B545 Winchester Disk Drive Support Logic August, 1988 INNOVATORS In / i NTEG RATION DESCRIPTION The SSI 32B545 is an integrated circuit which consoli dates functions in a W inchester Disk Drive normally performed by a variety of LSTTL SSI and MSI devices. Various , signal needs. The SSI 32B545 uses a single +5 volt supply and is available in 40 pin DIP and 44 pin PLCC , static sensitive component. SSI 32B545 Winchester Disk Drive Support Logic PIN DESCRIPTIONS PIN
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32B545
40-Pln
44-Pin
32B545-CH
40-Pin
SSI 280
ST506
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2008 - SSI 280
Abstract: No abstract text available
Text: Magnetic absolute multi-turn shaft encoder BMMV MAGRES hermetic SSI features · · · · · · multi-turn encoder / SSI magnetic principle, hermetically sealed resolution: single-turn 12 bit and , (at 24 VDC) (24C) SSI , RS 422 Gray and binary code 12 bit (1 step = 5' 16'') 13 bit (8'192 revolutions , . shaft load axial: 120 N radial: 280 N (combined) axial: 270 N (single load) product life max , BMMV 58 MAGRES hermetic SSI dimensions -5 ø 10 f6 20 10 0,5 M3 x 7 3 x 120° ø 60 3 3 25 36
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12/13H0
SSI 280
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mosfet to ignition coil
Abstract: USE OF TRANSISTOR ignition ignition coil IGBT MOSFET IGNITION IGNITION CONTROL MODULE 6 volt coil ignition spark ignition darlington transistor engine ignition ignition module IGBT automotive ignition coil on plug
Text: smiMfaiü' A TDK Group/Company DESCRIPTION The SSI 67F6612 is an integrated circuit designed to , large enough to create a voltage drop across Rs equal to the SSI 67F6612 internal dwell threshold (300 , is fired (SPIN pin is driven low). The SSI 67F6612-2 IN is a dual channel predriver. For greater cost and area savings, ignition systems may take advantage of the three channel SSI 67F6612-3IN orthe fourchannel 67F6612-4IL. All parts are available in plastic SO packages. SSI 67F6612 Dual/Triple/Quad
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67F6612
mosfet to ignition coil
USE OF TRANSISTOR ignition
ignition coil IGBT
MOSFET IGNITION
IGNITION CONTROL MODULE
6 volt coil ignition
spark ignition
darlington transistor engine ignition
ignition module IGBT
automotive ignition coil on plug
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aop 605
Abstract: MTP12 jwc 251 "tape storage"
Text: ABRIDGED VERSION A l óémóvskms A TDK Group/Company DESCRIPTION The SSI 34P3216A is a high , . Programmable functions of the SSI 34 P 3216A de vice are c o n tro lle d th ro u g h a b i directional serial port and banks of internal registers. The SSI 34P3216A utilizes an advanced BiCMOS process technology , consumption. The SSI 34P3216A supports a sleep mode for minimal power dissipation in no n-o pera tion al periods. The SSI 34P3216A provides a low noise read path with selectable gains of 50 V/V and 100 VA
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34P3216A
aop 605
MTP12
jwc 251
"tape storage"
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2005 - optical steering angle sensor
Abstract: No abstract text available
Text: output Interface output is SSI (2wire SSI / 3wire SSI ) with RS485 line transceiver or single ended , Digital Outputs Ouput-H-Level Output-L-Level SSI Serial Interface SCL Clock Frequency (3wire SSI ) SCL clock Frequency (2wire SSI ) Duty Cycle fclock Gray Code Monotony Error (1) SPI Serial Interface , , fcos With LED reg turns On 500 0.56 2.50 2.80 kHz V V Symbol Conditions Min. Typ. Max , -wire SSI Timing diagram (for single ended drive) Min Delay : 500 nS clock cycle NSL SCL DOUT MSB 1 MSB
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AEAT-9000-1GSH0
17-Bit
AEAT-9000
AV02-3130EN
optical steering angle sensor
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1998 - CXA2006Q
Abstract: CXD2311AR CXD2460R ICX205AK VOM101 VOM102
Text: 2 1/1068 1/267 29 SEN VSS1 10 Register VSS2 11 31 SSI VSS3 20 7 24 RST , HRO EXP ID SSI SSK SEN TEST2 2MCK VDD1 MCK Pin Configuration (Top View , . PS = Low: Serial setting clock input. 31 SSI I PS = High: Shutter speed setting input , RST, TEST2, Vt + 1 SEN, SSK, SSI , HRI, FRI, DSGAT Vt 1 0.8VDDa VOH1 Feed current where , AC Characteristics 1) AC characteristics between the serial interface clocks SSI 0.8VDDa
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CXD2460R
CXD2460R
636MHz
48PIN
LQFP-48P-L01
LQFP048-P-0707
42/COPPER
CXA2006Q
CXD2311AR
ICX205AK
VOM101
VOM102
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2005 - 17-BIT encoder
Abstract: AEAT-9000-1GSH0
Text: CPR A/B channel incremental digital output Interface output is SSI (2wire SSI / 3wire SSI ) with RS485 , Inputs Pull Up Current Pull down Current Digital Outputs Ouput-H-Level Output-L-Level SSI Serial Interface SCL Clock Frequency (3wire SSI ) SCL clock Frequency (2wire SSI ) Duty Cycle fclock Gray Code , Nominal -8 -15 -23 5 4 +8 +15 +28 Deg Deg Deg 2.20 fsin, fcos With LED reg turns On 500 0.56 2.50 2.80 kHz , +1 17 Min Delay > 20 S 1 MSB 2 MSB-1 LSB Figure 1a. 2-wire SSI Timing diagram (for single ended
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AEAT-9000-1GSH0
17-Bit
AEAT-9000
AV02-3130EN
17-BIT encoder
AEAT-9000-1GSH0
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2005 - Not Available
Abstract: No abstract text available
Text: A/B channel incremental digital output ⢠Interface output is SSI (2wire SSI / 3wire SSI ) with , Operating Currents Total Current 94 mA Digital Inputs Digital Outputs SSI Serial Interface SCL Clock Frequency (3wire SSI ) fclock 10 MHz SCL clock Frequency (2wire SSI ) fclock , (2) 2.20 kHz 0.56 Output Voltage Amplitude (2) V 2.50 2.80 V +8 Deg , 2 MSB-1 Figure 1a. 2-wire SSI Timing diagram (for single ended drive) Min Delay : ½ clock
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AEAT-9000-1GSH0
17-Bit
AEAT-9000
HEDS-8949
AV02-3130EN
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2005 - Not Available
Abstract: No abstract text available
Text: A/B channel incremental digital output ⢠Interface output is SSI (2wire SSI / 3wire SSI ) with , Operating Currents Total Current 94 mA Digital Inputs Digital Outputs SSI Serial Interface SCL Clock Frequency (3wire SSI ) fclock 10 MHz SCL clock Frequency (2wire SSI ) fclock , (2) 2.20 kHz 0.56 Output Voltage Amplitude (2) V 2.50 2.80 V +8 Deg , 2 MSB-1 Figure 1a. 2-wire SSI Timing diagram (for single ended drive) Min Delay : 500 nS
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AEAT-9000-1GSH0
17-Bit
AEAT-9000
HEDS-8949
AV02-3130EN
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2002 - ICX205
Abstract: S2513 AVD1 CXA2006Q CXD2311AR CXD2460R ICX205AK VOM101 VOM102
Text: 2 1/1068 1/267 29 SEN VSS1 10 Register VSS2 11 31 SSI VSS3 20 7 24 RST , HRO EXP ID SSI SSK SEN TEST2 2MCK VDD1 MCK Pin Configuration (Top View , . PS = Low: Serial setting clock input. 31 SSI I PS = High: Shutter speed setting input , RST, TEST2, Vt + 1 SEN, SSK, SSI , HRI, FRI, DSGAT Vt 1 0.8VDDa VOH1 Feed current where , AC Characteristics 1) AC characteristics between the serial interface clocks SSI 0.8VDDa
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CXD2460R
CXD2460R
636MHz
42/COPPER
48PIN
LQFP-48P-L01
P-LQFP48-7x7-0
ICX205
S2513
AVD1
CXA2006Q
CXD2311AR
ICX205AK
VOM101
VOM102
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Not Available
Abstract: No abstract text available
Text: SSI 32P4752/4756 ó é m M Ãm Read Channel with 1,7 ENDEC, 4-burst Servo " A TDK G roup/C om pany January 1995 DESCRIPTION FEATURES The SSI 32P4752/4756 devices are high , dual-bit parallel interface to the controller. GENERAL: Programmable functions of the SSI 32P4752 , from zone tozone. The SSI 32P4752/4756 utilize an advanced BiCMOS process technology along/ with , BLOCK DIAGRAM I V PA JV PB JV P C JV P D JV P D 2 ] VPG SSI 32P4752/4756 Read Channel with
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32P4752/4756
32P4752/4756
32P4752-CGT
32P4756
64-Lead
32P4756-CGT
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38dec
Abstract: 34P3400
Text:  SSI 34P3400 30 Mbit/s Read Channel w/Adaptive Threshold Qualifier Sum systems A TDK Group/Company DESCRIPTION The SSI 34P3400 device is a high performance BiCMOS single chip read channel IC that , digital commands without external component switching. The SSI 34P3400 allows complete flexibility in , cost zoned recording system can be implemented. The SSI 34P3400 utilizes an advanced BiCMOS process , ´Ã´ This Material Copyrighted By Its Respective Manufacturer SSI 34P3400 30 Mbit/s Read Channel w
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34P3400
34P3400
0195-rev.
A253TbS
D012D34
38dec
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Not Available
Abstract: No abstract text available
Text: SSI 34P3400 ¿ ik o n s y s te m 30 Mbit/s Read Channel w/Adaptive Threshold , SSI 34P3400 device is a high performance BiCMOS single chip read channel 1C that contains all the , W ) Power supply range (4.5 to 5.5V) The SSI 34P3400 allows complete flexibility in read , pensated, exponential control AGC The SSI 34P3400 utilizes an advanced BiCMOS process technology along , sensitive component. SSI 34P3400 30 Mbit/s Read Channel w/Adaptive Threshold Qualifier BLOCK DIAGRAM -
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34P3400
34P3400
flB531b5
0012D34
0195-rev.
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2005 - ssi protocol
Abstract: 17-BIT encoder
Text: CPR A/B channel incremental digital output Interface output is SSI (2wire SSI / 3wire SSI ) with RS485 , Inputs Pull Up Current Pull down Current Digital Outputs Ouput-H-Level Output-L-Level SSI Serial Interface SCL Clock Frequency (3wire SSI ) SCL clock Frequency (2wire SSI ) Duty Cycle fclock Gray Code , Nominal -8 -15 -23 5 4 +8 +15 +28 Deg Deg Deg 2.20 fsin, fcos With LED reg turns On 500 0.56 2.50 2.80 kHz , +1 17 Min Delay > 20 MS 1 MSB 2 MSB-1 LSB Figure 1a. 2-wire SSI Timing diagram (for single
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AEAT-9000-1GSH0
17-Bit
AEAT-9000
AV02-3130EN
ssi protocol
17-BIT encoder
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32p4752-cgt
Abstract: hdd ssi
Text: SSI 32P4752/4756 S ilic o n J u s fa n s A TDK Group/Company Read Channel with 1,7 ENDEC, 4-burst Servo October 1995 DESCRIPTION The SSI 32P4752/4756 devices are high performance BiCMOS single , the controller. Programmable functions of the SSI 32P4752/4756 devices are controlled through a , supported without changing external component values from zone to zone. The SSI 32P4752/4756 utilize an , : BLOCK DIAGRAM 0253*^5 Ö24 SSI 32P4752/4756 Read Channel with 1,7 ENDEC, 4-burst Servo
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32P4752/4756
32P4752/4756
64-Lead
32P4752-CGT
32P4756-CGT
32P4756-CGT
hdd ssi
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Not Available
Abstract: No abstract text available
Text: SSI 32P4752 ¿iconM km s A TDK Group/Company DESCRIPTION The SSI 32P4752 devices are high , parallel interface to the controller. Programmable functions of the SSI 32P4752 devices are controlled , applications to be supported without changing external component values from zone to zone. The SSI 32P4752 , precision full-w ave rectifier (continued) BLOCK DIAGRAM SSI 32P4752 Read Channel with 1,7 ENDEC, 4 , max. pulse pairing at 64 Mbit/s using a 6 MHz sine wave input FUNCTIONAL DESCRIPTION The SSI
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32P4752
32P4752
64-Lead
32P4752-CGT
32P4752-CGT
02S3TbS
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a2531
Abstract: 32F8130
Text: cwmMbtis' A TDK Group/Company SSI 32F8130/8131 Low-Power Programmable Electronic Filter January 1995 DESCRIPTION The SSI 32F8130/8131 Programmable Electronic Filters are digitally controlled , passband. The SSI 32F8130/8131 bandwidth and boost are controlled by two on-chip 7-bit DACs, which are programmed via a 3-line serial interface. The SSI 32F8130 filter bandwidth is programmable from 285 kHz to , , the flat group delay characteristic is not affected by the boost programming. The SSI 32F8130/8131
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32F8130/8131
32F8130/8131
32F8130
SSI32F8131
0195-rev.
a2531
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Not Available
Abstract: No abstract text available
Text: ¿mmáyskmsâ A TDK Group!Company SSI 32F8130/8131 Low-Power Programmable Electronic Filter January 1993 FEATURES DESCRIPTION The SSI 32F8130/8131 Programmable Electronic Fil ters are , response beyond the passband. Programmable filter cutoff frequency ( SSI 32F8130 FC=0.25 to 2.5 MHz, SSI , The SSI 32F8130/8131 bandwidth and boost are con trolled by two on-chip 7-bit DACs, which are pro grammed via a 3-line serial interface. The SSI 32F8130 filter bandwidth is programmable from 250 kHz to
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32F8130/8131
32F8130/8131
32F8130
32F8131:
32F8130-CL
32F8131-CL
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SSI 280
Abstract: 4X4X2 CD22101 CD22102 22102 switch RCA-CD22101
Text: 15 â 110 220 Ka ⢠Kb to Output, SSI 22102 5 â 280 560 10 â 130 260 15 â , mmsvskms INNOVATORS IN/INTEGRATION SSI 22101/22102 CMOS 4x4x2 Crosspoint Switches with Control Memory Data Sheet GENERAL DESCRIPTION The SSI 22101 and 22102 crosspoint switches consist of 4x4x2 , and off simultaneously, also. In the SSI 22101, the selected crosspoint pair can be turned on or off , succession. The selected pair of crosspoints in the SSI 22102 Is turned on by applying a logical ONE to the
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16-line
SSI 280
4X4X2
CD22101
CD22102
22102 switch
RCA-CD22101
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Not Available
Abstract: No abstract text available
Text: SSI 32F8130/8131 wmsiiskmsâ Low-Power Programmable Electronic Filter A TDK G ro u p /C o m pany January 1993 DESCRIPTION FEATURES The SSI 32F8130/8131 Programmable Electronic , flat group delay response beyond the passband. * Programmable filter cutoff frequency ( SSI 32F8130 FC=0.25 to 2.5 MHz, SSI 32F8131: FC =0.15 to 1.4 MHz) with no external components, serial data connections to mlnimze pin count * Power down mode (<5 mW) The SSI 32F8130/8131 bandwidth and boost
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32F8130/8131
32F8130/8131
32F8130
32F8131:
32F8130-CL
32F8131-CL
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